XRT94L31IB Exar Corporation, XRT94L31IB Datasheet - Page 56

• Manufacturer Part Number: XRT94L31IB
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
C19
TXHDLCDAT_1_5
STS1TXA_1_D5
SIGNAL NAME
TXDS3FP_1
I/O
I/O
TTL/
CMOS
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 1 - Input Data Bus
pin number 5/Transmit High-Speed HDLC Controller Input Interface
block - Channel 1 - Input Data Bus - Pin 5/Transmit DS3/E3 Frame
Boundary Indicator Output - Channel 1:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 1 is enabled.
If STS-1 Telecom Bus (Channel 1) has been enabled -Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 5:
STS1TXA_1_D5:
This input pin along with STS1TXA_1_D[7:6] and STS1TXA_1_D[4:0]
function as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data
Bus for Channel 1. The Transmit STS-1 Telecom Bus interface will sam-
ple and latch this pin upon the falling edge of STS1TXA_CLK_1.
been disabled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Channel 1 - Data Bus Input
pin # 5 -TXHDLCDAT_1_5:
If the XRT94L31 is configured to operate in the High-Speed HDLC Con-
troller over DS3/STS-3 Mode, then this input pin will function as Bit 5
within the Transmit High-Speed HDLC Controller Input Interface block -
Input Data Bus (e.g., the TxHDLCDat_1[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_1). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_1[7:0] input pins) upon the rising edge of the TxHDLCClk_1
clock output signal.
E3 Framer over STS-3/STM-1 Mapper Mode - Transmit DS3/E3
Frame Boundary Indicator Output - Channel 1 - TXDS3FP_1:
This output pin is pulse "High" for one DS3 or E3 clock period, when the
Transmit Payload Data Input Interface block of Channel 1 (within the
XRT94L31) is processing the last bit of a given DS3 or E3 frame.
If the STS-1 Telecom Bus Interface (associated with Channel 1) has
If the XRT94L31 is configured to operate in the Clear-Channel DS3/
56
DESCRIPTION
REV. 1.0.1