73M1903-IM/F Maxim Integrated Products, 73M1903-IM/F Datasheet
73M1903-IM/F
Specifications of 73M1903-IM/F
Related parts for 73M1903-IM/F
73M1903-IM/F Summary of contents
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... Simplifying System Integration DESCRIPTION The Teridian 73M1903 Analog Front End (AFE) IC includes fully differential hybrid driver outputs, which connect to the telephone line interface through a transformer-based DAA. The receive pins are also fully differential for maximum flexibility and performance. This arrangement allows for the ...
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... QFN Pinout ................................................................................................................ 33 9.2 20-Pin TSSOP Pinout ........................................................................................................... 34 10 Mechanical Specifications .......................................................................................................... 35 10.1 32-Pin QFN Mechanical Drawings ......................................................................................... 37 10.2 20-Pin TSSOP Mechanical Drawings .................................................................................... 38 11 Ordering Information ................................................................................................................... 39 Appendix A – 73M1903 DAA Resistor Calculation Guide .................................................................. 40 Appendix B – Crystal Oscillator .......................................................................................................... 42 Revision History .................................................................................................................................. 47 2 Table of Contents DS_1903_032 Rev. 2.1 ...
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... Figure 10: Frequency Response of TX Path for kHz in Band Signal ........................................... 21 Figure 11: Serial Port Data Timing ......................................................................................................... 28 Figure 12: 32-Pin QFN Pinout ................................................................................................................ 33 Figure 13: 20-Pin TSSOP Pin out .......................................................................................................... 34 Figure 14: 73M1903 Schematic ............................................................................................................. 35 Figure 14: 32-Pin QFN Mechanical Specifications .................................................................................. 37 Figure 15: 20-Pin TSSOP Mechanical Specifications ............................................................................. 38 Figure 16: NCO Block Diagram .............................................................................................................. 42 Figure 17: PLL Block Diagram ............................................................................................................... 43 Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ...
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... Data Sheet 1 Signal Description The Teridian 73M1903 modem AFE IC is available in a 20-pin TSSOP or 32-pin QFN package with the same pin out. The following table describes the function of each pin. There are two pairs of power supply pins, VPA (analog) and VPD (digital). They should be decoupled separately from the supply source in order to isolate digital noise from the analog circuits internal to the chip ...
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... Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h), ENFE=0. During the normal operation, a data FS is generated by the 73M1903 at the rate of Fs. For every data FS there are 16 bits transmitted and 16 bits received. The frame synchronization (FS) signal is pin programmable for type ...
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... SPOS is set the control frame is ¼ of the way between consecutive data frames, i.e., the control frame is closer to the first data frame. This is illustrated in New to the 73M1903 modem AFE feature that shuts off the serial clock (SCLK) after 32 cycles of SCLK following the frame synch option ...
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... DS_1903_032 32 Cycles of sclk SCLK FS(mode1) 32 Cycles of sclk SCLK FS(mode0) Figure 1: Effect of the TYPE (FS mode) pin on FS with SckMode = 0 Figure 2: Control Frame Position versus SPOS Rev. 2.1 SCLK and FS in mode 1 SCLK and FS in mode 0 73M1903 Data Sheet 7 ...
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... Data Sheet 2 Control and Status Registers Table 2 shows the memory map of addressable registers in the 73M1903. Each register and its bits are described in detail in the following sections. Address Default Bit 7 Bit 6 00 08h ENFE Unused 01 00h TMEN DIGLB 02 FFh GPIO7 GPIO 6 ...
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... DO7 Control Frame With Late Frame Sync 7.2KHz (8KHz Control Frame Relation Between the Data and Control Frames Figure 3: Serial Port Timing Diagram 73M1903 Data Sheet TX6 TX5 TX4 TX3 TX2 TX1 RX6 RX5 RX4 RX3 RX2 RX1 DI6 DI5 DI4 ...
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... The analog interface circuit uses differential transmit and receive signals to and from the external circuitry. The hybrid driver in the 73M1903 IC is capable of connecting directly, but not limited to, a transformer- based Direct Access Arrangement (DAA). The hybrid driver is capable of driving the DAA’s line coupling transformer, which carries an impedance on the primary side that is typically rated at 600 Ω ...
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... Figure 4: Analog Block Diagram Table 3: PLL Loop Filter Settings FL PLLloop Filter Settings R1=32 kΩ,C1=100 pF,C2=2 R1=16 kΩ, C1=100 pF,C2=2 Bit 4 Bit 3 Bit 2 Ndvsr4 Ndvsr3 Ndvsr2 Bit 4 Bit 3 Bit 2 Nseq4 Nseq3 Nseq2 73M1903 Data Sheet Bit 1 Bit 0 Ndvsr1 Ndvsr0 Bit 1 Bit 0 Nseq1 Nseq0 11 ...
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... Data Sheet 2.2.3 Control Register (CTRL 13): Address 0Dh Reset State 48h Bit 7 Bit 6 Bit 5 Xtal1 Xtal0 Reserved Reserved Unused 00 = Xtal osc. bias current at 120 μA Xtal[1: Xtal osc. bias current at 180 μ Xtal osc. bias current at 270 μ Xtal osc. bias current at 450 μA If OSCIN is used as a Clock input, “ ...
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... Ndvsr[6:0], Nseq[7:0], and Nrst[2:0]. The following is a brief description of the registers that control the NCOs, PLLs, and sample rates for the 73M1903 IC. The tables show some examples of the register settings for different clock and sample rates. A more detailed discussion on how these values ...
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... Data Sheet Addr. 00h bit 7 ENFE Nnco1 (kHz) Dnco1 7.2 8/125 15 8.0 8/125 15 2.4*8/7*3 8/169 =8.22857142858 21 8.4 8/125 15 9.0 8/125 15 9.6 8/125 15 2.4*10/7*3 8/125 =10.2857142857 15 2.4*8/7*4 7/50 =10.9714285714 7 11.2* 7/52 7 12.0 8/125 15 12.8* 8/65 8 2.4*10/7*4 7/80 =13.7142857143 11 14.4 8/125 15 7.2 ...
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... XX111110 5 7/145 11011010 7 5/168 XXXX1000 3 5/72 11011010 7 5/192 XXX10000 4 8/257 X1010100 6 6/173 10010010 73M1903 Data Sheet PllSeq(7:0) PllRst Fvco =Dnco2 (Mhz XXX11010 4 58.982400 57 XXX11010 4 66.355200 21 XXX11010 4 33.1776 19 XXX10000 4 36.864 28 XX111110 5 37.91781* 25 XXX10000 4 38.7072 10 XXX11110 4 41.472 28 XXX11110 4 44.2368 30 X1111110 6 47 ...
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... Data Sheet Table 8: Clock Generation Register Settings for Fxtal = 24.576 MHz Reg Address Fs (kHz) 2.4*8/7*3 =8.22857142858 2.4*10/7*3 =10.2857142857 2.4*8/7*4 =10.9714285714 11.2 12.8 2.4*10/7*4 =13.7142857143 14.4 Table 9: Clock Generation Register Settings for Fxtal = 9.216 MHz Address Fs (kHz) 2.4*8/7*4 =10.9714285714 11.2 12.8 14 ...
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... Xtal Oscillator NCO Prescaler Fxtal Rev Loop Filter Control VCO Locked Up Fref R1 Charge Kd C2 PFD Pump Ichp Control Kvco Control NCO Figure 5: Clock Generation 73M1903 Data Sheet Ichp Kvco (μA) [2: Ichp Kvco (μA) [2: FrcVco 0 System Clock 1 Fvco VCO Kvco 2 17 ...
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... Data Sheet 4 Modem Receiver A differential receive signal applied at the RXAP and RXAN pins or the output signal at TXAP and TXAN pass through a multiplexer, which selects the inputs to the ADC. In normal mode, RXAP/RXAN are selected. In analog loopback mode, TXAP/TXAN are selected. The DC bias for the RXAP/RXAN inputs is supplied from TXAP/TXAN through the external DAA in normal conditions ...
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... Vpk-diff each, respectively for Fs=8 kHz. Note the effect of FIR suppressing the noise above 4 kHz but at the same time enhancing (in order to compensate for the 3 passband droop of sinc filter) it near the passband edge of 4 kHz. Rev. 2.1 Figure 7: Rx Passband Response 73M1903 Data Sheet 19 ...
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... Data Sheet Figure 9: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes 20 Figure 8: RXD Spectrum of 1 kHz Tone DS_1903_032 Rev. 2.1 ...
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... TXD to TXAP/TXAN for kHz in-band signal including the effect of this sampling process plus those of DAC1, TLPF and SMFLT important to note that as TXD is sampled at 8 kHz band-limited to 4 kHz. Figure 10: Frequency Response of TX Path for kHz in Band Signal Rev. 2.1 73M1903 Data Sheet 21 ...
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... Data Sheet 5.1 Transmit Levels The 16-bit transmit code word written by the DSP to the Digital Sigma-Delta Modulator (DSDM) (via TIF) has a linear relationship with the analog output signal. So, decreasing a code word by a factor of 0.5 will result in a 0.5 (-6 dB) gain change in the analog output signal. ...
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... Crest Factor Max Line Level V.90 4.0 QAM 2.31 DPSK 1.81 FSK 1.41 DTMF 1.99 Bit 4 Bit 3 Bit 2 TXBST0 TXDIS RXG1 Table 12. 73M1903 Data Sheet . pk -12 dBm -9 dBm -9 dBm -9 dBm -5.7 dBm Bit 1 Bit 0 RXG0 RXGAIN 23 ...
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... Reset State 30h Bit 7 Bit 6 Bit 5 Rev3 Rev2 Rev1 Bits 7-4 contain the revision level of the 73M1903 device. The rest of this register is for chip development purposes only and is not intended for customer use. Do not write to shaded locations. 24 Bit 4 Bit 3 Bit 2 INTLB ...
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... Power Saving Modes The 73M1903 has only one power conservation mode. When the ENFE, bit 7 in register 0h, is zero the clocks to the filters and the analog are turned off. The transmit pins output a nominal 80 kΩ impedance. The clock to the serial port is running and the GPIO and other registers can be read or updated. ...
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... Data Sheet 8 Electrical Specifications 8.1 Absolute Maximum Ratings Operation above maximum rating may permanently damage the device. Parameter Supply Voltage Pin Input Voltage (except OSCIN) Pin Input Voltage (OSCIN) 8.2 Recommended Operating Conditions Parameter Supply Voltage (VDD) with respect to VSS ...
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... IIL1 VSS < Vin < VIL1 VIH1 < Vin < 5.5 IIL2 VSS < Vin < VIL2 VIH2 < Vin <VDD Fs=8 kHz, Xtal=27 MHz Fs=11.2 kHz, Xtal=27 MHz Fs=14.4 kHz, Xtal=27 MHz 73M1903 Data Sheet Min Nom Max -0.5 0.2 * VDD 5.5 VDD + 5.5 0.45 0.7 0.45 1 ...
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... Data Sheet 8.3.2 AC Timing Parameter SCLK Period (Tsclk) (Fs=8 kHz) SCLK to FS Delay (td1) – mode1 SCLK to FS Delay (td2) – mode1 SCLK to SDOUT Delay (td3) (With 10pf load) Setup Time SDIN to SCLK (tsu) Hold Time SDIN to SCLK (th) SCLK to FS Delay (td4) – mode0 SCLK to FS Delay (td5) – ...
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... Test Condition Min 40* Table 16: Maximum Transmit Levels Maximum Single- Peak to Ended Level at rms Ratio TXA Pins (dBm) 4 -11.0 -6.3 -4.1 -2.0 -6.8 -8.8 73M1903 Data Sheet Nom Max Units 1.36 V -86 -80 dBm 600 dB Single-Ended Single-Ended rms Voltage at Peak Voltage TXA Pins (V) at TXA Pins (v) 0 ...
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... Data Sheet 8.5 Performance 8.5.1 Receiver Table 17: Receiver Performance Specifications Parameter Input Impedance Measured at RXAP/N relative to VREF RXPULL=HI Measured at RXAP/N relative to VREF RXPULL=LO Receive Gain Rxgain = 1; 1 kHz; RXAP/N=0.116 V Boost Gain Measured relative to Rxgain=0 RXGAIN=1 for Fs=8 kHz RXGAIN =1 for Fs=12 kHz RXGAIN =1 for Fs=14 ...
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... Transmit Gain Gain at 0.5 kHz Flatness Gain at 1 kHz (Normalized) Gain at 2.0 kHz Gain at 3.3 kHz Rev. 2.1 Test Condition nd and rd harmonic. rd harmonic and 3 harmonic (-2 dBm tone summed with 73M1903 Data Sheet Min Nom Max Units µv/bit 70 -100 100 mV - 1.65 dB 1.335 dB -75 -85 ...
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... Data Sheet Parameter Test Condition TXAP/N Output TXDIS=1 Impedance Measure impedance differentially Differentially between TXAP and TXAN. (TXDIS=1) TXAP/N Common TXDIS=1 Output Offset Short TXAP and TXAN. Measure the (TXDIS=1) voltage respect to Vbg. Note: TXBST0 and DTMFBS are assumed to have setting 0’s unless they are specified otherwise. ...
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... VPD 18 GPIO0 19 GPIO1 20 GPIO2 21 GPIO3 SCLK 24 RST 25 VPA 26 TXAN 27 TXAP 28 VREF 29 RXAN 30 RXAP 31 VNA 32 73M1903 Data Sheet GPIO5 24 23 GPIO4 22 VND 21 N/C 20 VPPLL 19 OSCIN OSCOUT 18 17 VNPLL Name VNPLL OSCOUT OSCIN VPPLL CLKOUT VND GPIO4 GPIO5 VPD N/C TYPE SckMode SDIN ...
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... Data Sheet 9.2 20-Pin TSSOP Pinout SDOUT VND VPD FS SCLK VREF RST VPA TXAN TXAP Pin 73M1903 Figure 13: 20-Pin TSSOP Pin out Table 20: 20-Pin TSSOP Pin Definitions Name Pin SDOUT 11 VND 12 VPD SCLK 15 VREF 16 RST 17 VPA 18 TXAN 19 TXAP 20 DS_1903_032 SDIN ...
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... DS_1903_032 10 73M1903 Schematic and Bill of Material RESET\ RESET SCLK FS\ SDO VCCD C10 C9 + 0.1uF 3.3uF 73M1903-20VT U1 SDI VCCD C11 0.1uF 27MHz or other SY SCLK R16 100 HOOK f rom host Rev. 2.1 R17 38.3K, 1% VCCA R48 210, 1% ISOLATION BARRIER C4 R20 2.2nF 61.9K C21 0.15uF 20K 0 ...
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... Data Sheet Item Qty Reference 1 1 BR1 C10,C11,C13,C21 7 1 C19 8 2 C20,C23 9 1 C22 L1, R16 16 2 R17,R22 17 2 R20,R23 18 2 R48,R49 Table 21: Bill of Materials Part 400 V, 500 mA Bridge Rectifier 0.15 µ 2 µF 6.3 V 3.3 µF 6.3 V 0.1 µ 0.22 µF 250 V ...
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... Dimensions in mm TOP VIEW 0.2 MIN. 0.35 / 0.45 Figure 15: 32-Pin QFN Mechanical Specifications Rev. 2.1 / 0.85 NOM. 0.9MAX. 2.5 3.0 / 3.75 0.18 / 0.3 1.5 / 1.875 0.25 0.5 BOTTOM VIEW 73M1903 Data Sheet 0.00 / 0.005 0.20 REF. SEATING PLANE SIDE VIEW CHAMFERED 0. ...
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... Data Sheet 11.2 20-Pin TSSOP Mechanical Drawings Dimensions in mm. Figure 16: 20-Pin TSSOP Mechanical Specifications 38 DS_1903_032 Rev. 2.1 ...
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... QFN Lead Free 73M1903 32-Lead QFN, Tape and Reel, Lead Free 73M1903 20-Lead TSSOP Lead Free 73M1903 20-Lead TSSOP, Tape and Reel, Lead Free Rev. 2.1 Table 22: Ordering Information Order Number 73M1903-IM/F 73M1903-IMR/F 73M1903-IVT/F 73M1903-IVTR/F 73M1903 Data Sheet Package Mark 73M1903-M ...
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... Data Sheet Appendix A – 73M1903 DAA Resistor Calculation Guide The following procedure is used to approximate the component values for the DAA. The optimal values will be somewhat different due to the effects of the reactive components in the DAA (this approximation). Simulations with the reactive components accurately modeled will yield optimal values. ...
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... IC. This definition is only valid when driving a specific phone line impedance. In reality, phone line impedances are never perfect, so this definition isn’t of much help. Instead alternate definition that helps in analysis for this modem design, THL is the loss from the transmit pins to the receive pins. Rev. 2.1 73M1903 Data Sheet 41 ...
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... Data Sheet Appendix B – Crystal Oscillator The crystal oscillator is designed to operate over wide choice of crystals (from 9 MHz to 27 MHz). The crystal oscillator output is input to an NCO based pre-scaler (divider) prior to being passed onto an on- chip PLL. The intent of the pre-scaler is to convert the crystal oscillator frequency, Fxtal convenient frequency to be used as a reference frequency, Fref, for the PLL. A set of three numbers– ...
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... Ndvsr = Integer [ Fvco/Fref ] = 19 Nrst = 5 – from Fvco/Fref = 19.2 = 96/5; Nseq = ÷19, ÷19, ÷19, ÷19, ÷20 => {0,0,0,0,1} =xxx00001 = 01h. Rev. 2 Charge Kd C2 Pump Kvco Control NCO Figure 18: PLL Block Diagram Figure 18. The architecture of the 73m1903 73M1903 Data Sheet Divide VCO by 2/1 Kvco 3 43 ...
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... Three separate controls are provided to fine tune the PLL as shown in the following sections. To ensure quick settling of PLL, a feature was designed into the 73m1903 where Ichp is kept at a higher value until lokdet becomes active or Frcvco bit is set to 1, whichever occurs first. Thus PLL is guaranteed to have the settling time of less than one frame synch period after a new set of NCO parameters had been written to the appropriate registers ...
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... Pseq = {x,x,x,x,1,1,1,0} = xDh. PLL NCO: From Nnco2/Dnco2 = 1/18, Ndvsr = Integer [ Dnco2/Nnco2 ] = 18; Nrst[2:0] = Nnco2 – this means NO fractional divide. It always does ÷18. Thus Pseq becomes “don’t care”. Nseq = {x,x,x,x,x,x,x,x} = xxh. Rev. 2.1 • • 2.4kHz 8 576 MHz 18 • 73M1903 Data Sheet 45 ...
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... Data Sheet Example 3: Crystal Frequency = 27 MHz; Desired Sampling Rate 7.2 kHz Step 1. First compute the required VCO frequency, Fvco, corresponding 2.4 kHz 7.2 kHz. Fvco = 2 x 2304 2304 x 2.4 kHz 33.1776 MHz. Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers. ...
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... Removed the leaded package option. Changed the bottom view package dimension for 32-QFN package. Removed all references to the 32-pin TQFP package. Formatted to the new corporate standard. Added the schematic and bill of materials in Formatted to the new corporate standard. 73M1903 Data Sheet Section 10. 47 ...