MCP4441-103E/ST Microchip Technology, MCP4441-103E/ST Datasheet - Page 46
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
MCP4441-103E/ST
Manufacturer Part Number
MCP4441-103E/ST
Description
IC DGTL POT 129TAPS QUAD 20TSSOP
Manufacturer
Microchip Technology
Datasheet
1.MCP4441-103EML.pdf
(100 pages)
Specifications of MCP4441-103E/ST
Taps
129
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
150 ppm/°C Typical
Memory Type
Non-Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP (0.173", 4.40mm Width)
End To End Resistance
10kohm
Track Taper
Linear
Resistance Tolerance
± 20%
No. Of Steps
129
Supply Voltage Range
2.7V To 5.5V
Control Interface
I2C
No. Of Pots
Quad
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP4441-103E/ST
Manufacturer:
TAIYO
Quantity:
184 000
Company:
Part Number:
MCP4441-103E/ST
Manufacturer:
Microchip Technology
Quantity:
135
MCP444X/446X
4.2.2.2
There are two Terminal Control (TCON) Registers.
These are called TCON0 and TCON1. Each register
contains 8 control bits, four bits for each Wiper.
Register 4-2
while
register.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connection (A, B and W) can be individually connected/
disconnected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
DS22265A-page 46
Register 4-3
describes each bit of the TCON0 register,
Terminal Control (TCON) Registers
describes each bit of the TCON1
The value that is written to the specified TCON register
will appear on the appropriate resistor network
terminals when the serial command has completed.
When the WL1 bit is enabled, writes to the TCON0
register bits R1HW, R1A, R1W, and R1B are inhibited.
When the WL0 bit is enabled, writes to the TCON0
register bits R0HW, R0A, R0W, and R0B are inhibited.
When the WL3 bit is enabled, writes to the TCON1
register bits R3HW, R3A, R3W, and R3B are inhibited.
When the WL2 bit is enabled, writes to the TCON1
register bits R2HW, R2A, R2W, and R2B are inhibited.
On a POR/BOR these registers are loaded with
1FFh (9-bit), for all terminals connected. The Host
Controller needs to detect the POR/BOR event and
then update the Volatile TCON register values.
© 2010 Microchip Technology Inc.