MCP4461T-104E/ST Microchip Technology, MCP4461T-104E/ST Datasheet - Page 46

• Manufacturer Part Number: MCP4461T-104E/ST
• Description: IC DGTL POT 257TAPS 100K 20TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP4461T-104E/ST

• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Temperature Coefficient: 150 ppm/°C Typical
• Taps: 257
• Resistance (ohms): 100K
• Number Of Circuits: 4
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Pots: Quad
• Taps Per Pot: 257
• Resistance: 100 KOhms
• Wiper Memory: Non Volatile
• Buffered Wiper: Buffered
• Digital Interface: I2C
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Current: 600 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: Quad I2C Digital POT with Nonvolatile Memory
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP444X/446X
4.2.2.2
There are two Terminal Control (TCON) Registers.
These are called TCON0 and TCON1. Each register
contains 8 control bits, four bits for each Wiper.
Register 4-2
while
register.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connection (A, B and W) can be individually connected/
disconnected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
DS22265A-page 46
Register 4-3
describes each bit of the TCON0 register,
Terminal Control (TCON) Registers
describes each bit of the TCON1
The value that is written to the specified TCON register
will appear on the appropriate resistor network
terminals when the serial command has completed.
When the WL1 bit is enabled, writes to the TCON0
register bits R1HW, R1A, R1W, and R1B are inhibited.
When the WL0 bit is enabled, writes to the TCON0
register bits R0HW, R0A, R0W, and R0B are inhibited.
When the WL3 bit is enabled, writes to the TCON1
register bits R3HW, R3A, R3W, and R3B are inhibited.
When the WL2 bit is enabled, writes to the TCON1
register bits R2HW, R2A, R2W, and R2B are inhibited.
On a POR/BOR these registers are loaded with
1FFh (9-bit), for all terminals connected. The Host
Controller needs to detect the POR/BOR event and
then update the Volatile TCON register values.
© 2010 Microchip Technology Inc.