XC3S100E-4VQ100I Xilinx Inc, XC3S100E-4VQ100I Datasheet - Page 129
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XC3S100E-4VQ100I
Manufacturer Part Number
XC3S100E-4VQ100I
Description
IC FPGA SPARTAN 3E 100VQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S100E-4VQ100I
Number Of Logic Elements/cells
2160
Number Of Labs/clbs
240
Total Ram Bits
73728
Number Of I /o
66
Number Of Gates
100000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
100-TQFP
Package
100VTQFP
Family Name
Spartan®-3E
Device Logic Cells
2160
Device Logic Units
240
Device System Gates
100000
Number Of Registers
1920
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
66
Ram Bits
73728
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S100E-4VQ100I
Manufacturer:
MOLEX
Quantity:
10 000
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Table 88: Setup and Hold Times for the IOB Input Path
Table 89: Sample Window (Source Synchronous)
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
Setup Times
T
T
Hold Times
T
T
Set/Reset Pulse Width
T
T
Symbol
Symbol
IOPICK
IOPICKD
IOICKP
IOICKPD
RPW_IOB
SAMP
The numbers in this table are tested using the methodology presented in
Table 77
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from
edge.
R
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop
(IFF). No Input Delay is
programmed.
Time from the setup of data at the
Input pin to the active transition at the
IFF’s ICLK input. The Input Delay is
programmed.
Time from the active transition at the
IFF’s ICLK input to the point where
data must be held at the Input pin. No
Input Delay is programmed.
Time from the active transition at the
IFF’s ICLK input to the point where
data must be held at the Input pin.
The Input Delay is programmed.
Minimum pulse width to SR control
input on IOB
and
Setup and hold capture window of
an IOB input flip-flop
Table
80.
Description
Description
Table
Table
91.
91. When the hold time is negative, it is possible to change the data before the clock’s active
LVCMOS25
IFD_DELAY_VALUE = 0
LVCMOS25
IFD_DELAY_VALUE =
default software setting
LVCMOS25
IFD_DELAY_VALUE = 0
LVCMOS25
IFD_DELAY_VALUE =
default software setting
The input capture sample window value is highly specific to a
particular application, device, package, I/O standard, I/O
placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx application note for application-specific
values.
• XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at
Speeds Up to 666 Mbps
Conditions
www.xilinx.com
(2)
(2)
(2)
(2)
,
,
,
,
Table 95
VALUE=
DELAY_
IFD_
and are based on the operating conditions set forth in
0
2
3
0
2
3
Max
XC3S100E
XC3S100E
All Others
All Others
Device
DC and Switching Characteristics
All
All
All
–0.76
–3.93
–3.50
1.84
6.12
6.76
1.57
Min
Speed Grade
-5
–0.76
–3.93
–3.50
2.12
7.01
7.72
1.80
Min
-4
Units
Units
ps
ns
ns
ns
ns
ns
129
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