XC2V40-5FG256I Xilinx Inc, XC2V40-5FG256I Datasheet - Page 24

• Manufacturer Part Number: XC2V40-5FG256I
• Description: IC FPGA VIRTEX-II 256FGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V40-5FG256I

• Number Of Labs/clbs: 64
• Total Ram Bits: 73728
• Number Of I /o: 88
• Number Of Gates: 40000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

Shift Registers
Each function generator can also be configured as a 16-bit
shift register. The write operation is synchronous with a
clock input (CLK) and an optional clock enable, as shown in
Figure
4-bit address bus, A[3:0]. The configurable 16-bit shift regis-
ter cannot be set or reset. The read is asynchronous, how-
ever the storage element or flip-flop is available to
implement a synchronous read. The storage element
should always be used with a constant address. For exam-
ple, when building an 8-bit shift register and configuring the
addresses to point to the 7th bit, the 8th bit can be the
flip-flop. The overall system performance is improved by
using the superior clock-to-out of the flip-flops.
An additional dedicated connection between shift registers
allows connecting the last bit of one shift register to the first
bit of the next, without using the ordinary LUT output. (See
Figure
access to any bit in the chain. The shift register chaining
and the MUXF5, MUXF6, and MUXF7 multiplexers allow up
to a 128-bit shift register with addressable access to be
implemented in one CLB.
DS031-2 (v3.5) November 5, 2007
Product Specification
CE (SR)
D(BY)
A[3:0]
SHIFTIN
CLK
21. A dynamic read access is performed through the
22.) Longer shift registers can be built with dynamic
Figure 21: Shift Register Configurations
R
4
WE
CK
A[4:1]
WS
SRLC16
WSG
SHIFT-REG
MC15
DI
D
SHIFTOUT
(optional)
D
Q
DS031_05_110600
Output
Registered
Output
www.xilinx.com
Virtex-II Platform FPGAs: Functional Description
1 Shift Chain
in CLB
SRLC16
SRLC16
SRLC16
SRLC16
Figure 22: Cascadable Shift Register
DI
DI
DI
DI
MC15
MC15
MC15
MC15
SHIFTIN
SHIFTIN
D
D
D
D
SLICE S3
SLICE S2
IN
SHIFTOUT
OUT
FF
FF
FF
FF
CASCADABLE OUT
SLICE S1
SLICE S0
DI
SRLC16
SRLC16
SRLC16
SRLC16
DI
DI
SHIFTIN
DI
MC15
MC15
MC15
MC15
D
D
D
D
SHIFTOUT
SHIFTOUT
DS031_06_110200
Module 2 of 4
FF
FF
FF
FF
CLB
16