XC2V80-5FG256I Xilinx Inc, XC2V80-5FG256I Datasheet - Page 67

• Manufacturer Part Number: XC2V80-5FG256I
• Description: IC FPGA VIRTEX-II 256FGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V80-5FG256I

• Number Of Labs/clbs: 128
• Total Ram Bits: 147456
• Number Of I /o: 120
• Number Of Gates: 80000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

Table 19: Output Delay Measurement Methodology
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1.
2.
3.
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
SSTL, Class I, 3.3V
SSTL, Class II, 3.3V
AGP-2X/AGP (Accelerated Graphics Port)
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS, 3.3V
LVDSEXT (LVDS Extended Mode), 2.5V
LVDSEXT, 3.3V
BLVDS (Bus LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V
LVDCI/HSLVDCI
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI/HSLVDCI, 2.5V
LVDCI/HSLVDCI, 1.8V
LVDCI/HSLVDCI, 1.5V
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI
HSTL, Class III & IV, with DCI
HSTL, Class I & II, 1.8V, with DCI
HSTL, Class III & IV, 1.8V, with DCI
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI
SSTL, Class I & II, 2.5V, with DCI
SSTL, Class I & II, 3.3V, with DCI
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
C
Per PCI specifications.
Per PCI-X specifications.
REF
is the capacitance of the probe, nominally 0 pF.
R
Description
www.xilinx.com
HSTL_III_DCI_18, HSTL_IV_DCI_18
HSTL_I_DCI_18, HSTL_II_DCI_18
SSTL18_I_DCI, SSTL18_II_DCI
Virtex-II Platform FPGAs: DC and Switching Characteristics
SSTL2_I_DCI, SSTL2_II_DCI
SSTL3_I_DCI, SSTL3_II_DCI
HSTL_III_DCI, HSTL_IV_DCI
HSTL_I_DCI, HSTL_II_DCI
AGP-2X/AGP (falling edge)
AGP-2X/AGP (rising edge)
LVDCI_33, HSLVDCI_33
LVDCI_25, HSLVDCI_25
LVDCI_18, HSLVDCI_18
LVDCI_15, HSLVDCI_15
IOSTANDARD
LVDSEXT_25
LVDSEXT_33
LVPECL_33
BLVDS_25
GTLP_DCI
SSTL18_II
SSTL18_I
Attribute
SSTL2_II
SSTL3_II
LVDS_25
LVDS_33
GTL_DCI
SSTL2_I
SSTL3_I
LDT_25
R
(Ω)
1M
1M
1M
1M
1M
1M
50
25
50
25
50
25
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
REF
C
(pF)
REF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.94
2.03
1.23
1.65
1.25
0.75
MEAS
(V)
0.9
1.2
0.9
1.1
0.8
1.0
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Module 3 of 4
V
1.25
1.25
0.75
1.25
(V)
0.9
0.9
1.5
1.5
3.3
1.2
1.2
1.2
1.2
0.6
1.5
0.9
1.8
0.9
1.5
1.2
1.5
REF
0
0
0
0
0
0
0
19