XC4VLX160-10FF1148I Xilinx Inc, XC4VLX160-10FF1148I Datasheet - Page 8

• Manufacturer Part Number: XC4VLX160-10FF1148I
• Description: IC FPGA VIRTEX-4LX 1148FFBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VLX160-10FF1148I

• Number Of Logic Elements/cells: 152064
• Number Of Labs/clbs: 16896
• Total Ram Bits: 5308416
• Number Of I /o: 768
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1148-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-4 Documentation
Complete and up-to-date documentation of the Virtex-4
family of FPGAs is available on the Xilinx web site. In addi-
tion to the most recent Virtex-4 Family Overview, the follow-
ing files are also available for download:
Virtex-4 FPGA Data Sheet: DC and Switching
Characteristics
This data sheet contains the DC and Switching Characteris-
tic specifications for the Virtex-4 family.
Virtex-4 FPGA User Guide
This guide includes chapters on:
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XtremeDSP for Virtex-4 FPGAs User Guide
This guide describes the DSP48 slice and includes refer-
ence designs for using DSP48 math functions and various
FIR filters.
Revision History
The following table shows the revision history for this document.
DS112 (v3.1) August 30, 2010
Product Specification
08/02/04
09/10/04
12/08/04
03/26/05
06/17/05
02/10/06
10/10/06
01/23/07
Clocking Resources
Digital Clock Manager (DCM)
Phase-Matched Clock Dividers (PMCD)
Block RAM and FIFO memory
Configurable Logic Blocks (CLBs)
SelectIO Resources
SelectIO Logic Resources
Advanced SelectIO Logic Resources
Date
R
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
2.0
Initial Xilinx release. Printed Handbook version.
Typographical edits.
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Added note to
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Revision number jumped to 2.0 to correlate to data sheet (DS302) major revision.
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Removed System Monitor and ADC references.
Removed legacy CLB reference and typographical edits.
Removed FCRAM-II support.
Added stepping to order information example in
Changed maximum transceiver rate to 6.5 Gb/s.
Removed FF1760 package from
Table
Table
Edited Ethernet MAC section.
Edited serial transceiver sections.
In
Added note 3 to
Revised the CLB numbers for XC4VFX40 devices in
Table 2
1: Corrected typo: XC4VFX40 number of slices = 18,624.
2: Added column for FF676 package. Rewrote table footnotes.
added FFG Pb-Free packages.
Table 2
Table
for SparseChevron pinouts.
www.xilinx.com
1.
Virtex-4 FPGA Configuration Guide
This all-encompassing configuration guide includes chap-
ters on configuration interfaces (serial and SelectMAP), bit-
stream encryption, Boundary-Scan and JTAG configuration,
and reconfiguration techniques.
Virtex-4 FPGA Packaging and Pinout Specification
This specification includes the tables for device/package
combinations and maximum I/Os, pin definitions, pinout
tables, pinout diagrams, mechanical drawings, and thermal
specifications.
Virtex-4 FPGA PCB Designer’s Guide
This guide describes PCB guidelines for the Virtex-4 family.
It covers SelectIO signaling, RocketIO signaling, power dis-
tribution systems, PCB breakout, and parts placement.
Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide
This guide describes the RocketIO Multi-Gigabit Transceiv-
ers available in the Virtex-4 FX family.
Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User
Guide
This guide describes the Embedded Tri-Mode Ethernet
Media Access Controller available in the Virtex-4 FX family.
PowerPC 405 Processor Block Reference Guide
This guide is updated to include the PowerPC 405 proces-
sor block available in the Virtex-4 FX family.
Table
Revision
2.
Figure
Table
1.
1.
Virtex-4 Family Overview
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