XC2V8000-5FF1517I Xilinx Inc, XC2V8000-5FF1517I Datasheet - Page 47

• Manufacturer Part Number: XC2V8000-5FF1517I
• Description: IC FPGA VIRTEX-II 1517FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V8000-5FF1517I

• Number Of Labs/clbs: 11648
• Total Ram Bits: 3096576
• Number Of I /o: 1108
• Number Of Gates: 8000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

DS031-2 (v3.5) November 5, 2007
Product Specification
07/16/02
09/26/02
12/06/02
05/07/03
06/19/03
08/01/03
10/14/03
03/29/04
06/24/04
03/01/05
11/05/07
Date
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Version
2.1.1
2.1.2
2.0
2.1
2.2
3.0
3.1
3.2
3.3
3.4
3.5
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All Virtex-II devices and speed grades now Production. See Table 13, Module 3.
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Updated copyright statement and legal disclaimer.
Boundary-Scan (JTAG, IEEE 1532) Mode, page
statement.
Updated compatible input standards listed in Table 6.
Cosmetic edits.
Removed Compatible Output Standards and Compatible Input Standards tables.
Added new
Output
Added section
Added section
Table 1, page
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Reassigned heading hierarchies for better agreement with content.
Changed number of resources available to the XC2V40 device in
Clarified Power On Reset information under
Added qualification note to
Corrected sentence in section
optional weak-keeper circuit is connected to each user I/O pad.”
Corrected typographical errors in
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Table 2, page
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Table 3, page
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Sections
"falling" edge with respect to DOUT.
Added verbiage to section
this feature, please contact your sales representative for specific ordering part
number.”
Table 2, page
LVDSEXT_33_DCI from tables.
Table 26, page
Section
to be I0 or I1. Corrected signal names in
CLK1 to I0 and I1.
Recompiled for backward compatibility with Acrobat 4 and above.
Table 1, page
GTLP.
Added reference to Pb-free package types in
Table
Table
Added SSTL18_I and SSTL18_II.
Corrected names of 1.8V HSTL_I-IV standards to “HSTL_I-IV_18”.
Corrected Input V
Changed “N/A” to “N/R” (no requirement).
Changed “N/A” to “N/R” (no requirement).
Added SSTL18_I_DCI, SSTL18_II_DCI, LVDS_33_DCI, LVDSEXT_33_DCI,
LVDS_25_DCI, and LVDSEXT_25_DCI.
Corrected Input V
2: Corrected V
26: Updated bitstream lengths.
Standards. This table replaces deleted I/O standards tables.
BUFGMUX, page
Slave-Serial Mode
Table
1:
2:
2:
2, and
1: Added example to Footnote (1) regarding V
Rules for Combining I/O Standards in the Same Bank, page
Local Clocking, page
37: Updated bitstream lengths.
5,
www.xilinx.com
Summary of Voltage Supply Requirements for All Input and
OD
Table 5, page
REF
REF
output voltages.
for HSTL_III-IV_18 from 1.08V to 1.1V.
for HSTL_III-IV_18 from 1.08V to 1.1V.
29: Corrected the definition of the "presently selected clock"
Bitstream Encryption, page
Figure 13, page
and
Input/Output Individual Options, page
Master-Serial Mode, page
Table 3
Virtex-II Platform FPGAs: Functional Description
7: Removed LVDS_33_DCI and
Revision
29.
Figure 44
for names of HSTL_[x]_DCI_18 standards.
11.
Configuration
Figure 7, page
37: Updated IEEE 1149.1 compliance
and associated text from CLK0 and
38: “For devices that support
Sequence.
36: Changed "rising" to
CCO
6.
rules for GTL and
Table
4, to read “The
13.
Module 2 of 4
6.
39