M058ZAN Nuvoton Technology Corporation of America, M058ZAN Datasheet - Page 38
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M058ZAN
Manufacturer Part Number
M058ZAN
Description
IC MCU 32BIT 32KB FLASH 33QFN
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro M051™r
Specifications of M058ZAN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 5x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
33-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M058ZAN
Manufacturer:
NuvoTon
Quantity:
7 600
Part Number:
M058ZAN
Manufacturer:
NUVOTON
Quantity:
20 000
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Peripheral Reset Control Register1 (IPRSTC1)
Register
IPRSTC1
Bits
[31:4]
[3]
[2]
[1]
31
23
15
7
NuMicro M051
Offset
GCR_BA+08
Descriptions
Reserved
EBI_RST
Reserved
CPU_RST
30
22
14
6
Reserved
R/W
R/W
Reserved
EBI Controller Reset
Set these bit “1” will generate a reset signal to the EBI. User need to set this bit to “0” to
release from the reset state
This bit is the protected bit. It means programming this needs to write “59h”, “16h”, “88h”
to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100.
0= Normal operation
1= EBI IP reset
Reserved
CPU kernel one shot reset.
Set this bit will reset the Cortex-M0 CPU kernel and Flash memory controller (FMC). This
bit will automatically return to “0” after the 2 clock cycles
This bit is the protected bit. It means programming this needs to write “59h”, “16h”, “88h”
to address 0x5000_0100 to disable register protection. Reference the register
29
21
13
5
™
Description
Peripheral Reset Control Resister 1
Series Technical Reference Manual
28
20
12
4
- 38 -
Reserved
Reserved
Reserved
EBI_RST
27
19
11
3
Publication Release Date: Sep 14, 2010
Reserved
26
18
10
2
CPU_RST
25
17
9
1
Revision V1.2
Reset Value
0x0000_000
0
CHIP_RST
24
16
8
0
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