M0516ZAN Nuvoton Technology Corporation of America, M0516ZAN Datasheet - Page 234

• Manufacturer Part Number: M0516ZAN
• Description: IC MCU 32BIT 64KB FLASH 33QFN
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M0516ZAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 5x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 33-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

™
NuMicro M051
Series Technical Reference Manual
Slave Select
In master mode, this SPI controller can drive one off-chip slave device through the slave select
output pin SPISS. In slave mode, the off-chip master device drives the slave select signal from
the SPISS input port to this SPI controller. In master/slave mode, the active level of slave select
signal can be programmed to low active or high active in SS_LVL bit (SPI_SSR [2]), and the
SS_LTRIG bit (SPI_SSR [4]) define the slave select signal SPISS is level trigger or edge trigger.
The selection of trigger condition depends on what type of peripheral slave/master device is
connected.
Level-trigger / Edge-trigger
In slave mode, the slave select signal can be configured as level-trigger or edge-trigger. In edge-
trigger, the data transfer starts from an active edge and ends on an inactive edge. If master does
not send an inactive edge to slave, the transfer procedure will not be completed and the interrupt
flag of slave will not be set. In level-trigger, the following two conditions will terminate the transfer
procedure and the interrupt flag of slave will be set. The first condition, if master set the slave
select pin to inactive level, it will force slave device to terminate the current transfer no matter how
many bits have been transferred and the interrupt flag will be set. User can read the status of
LTRIG_FLAG bit to check if the data has been completely transferred. The second condition is
that if the number of transferred bits matches the settings of TX_NUM and TX_BIT_LEN, the
interrupt flag of slave will be set.
Automatic Slave Select
In master mode, if the bit AUTOSS(SPI_SSR[3]) is set, the slave select signal will be generated
automatically and output to SPISS pin according to SSR[0] (SPI_SSR[0]) whether be enabled or
not. It means that the slave select signal, which is enabled in SSR [0] register is asserted by the
SPI controller when transmit/receive is started by setting the GO_BUSY bit (SPI_CNTRL [0]) and
is de-asserted after the data transfer is finished. If the AUTOSS bit is cleared, the slave select
output signal is asserted and de-asserted by manual setting and clearing the related bit in
SPI_SSR [0] register. The active level of the slave select output signal is specified in SS_LVL bit
(SPI_SSR [2]).
Serial Clock
In master mode, set the DIVIDER (SPI_DIVIDER [15:0]) register to program the output frequency
of serial clock to the SPICLK output port. It also supports the variable frequency function if the
VARCLK_EN bit (SPI_CNTRL[23]) is enabled, in this case the each bit output frequency of serial
clock can be programmed at one frequency of two different frequencies which depend on the
DIVIDER and DIVIDER2 (SPI_DIVIDER[31:16]) settings. The decision of the variable frequency
for each bit is defined in VARCLK (SPI_VARCLK [31:0]) register. In slave mode, the off-chip
master device drives the serial clock through the SPICLK input port to this SPI controller.
Clock Polarity
The CLKP bit (SPI_CNTRL [11]) defines the serial clock idle state in master mode only. If CLKP =
1, the output SPICLK is idle at high state, otherwise it is at low state if CLKP = 0. For variable
serial clock, it works in CLKP = 0 only.
Publication Release Date: Sep 14, 2010
- 234 -
Revision V1.2