M0516LAN Nuvoton Technology Corporation of America, M0516LAN Datasheet - Page 246
![IC MCU 32BIT 64KB FLASH 48LQFP](/photos/28/73/287346/m0516lan_sml.jpg)
M0516LAN
Manufacturer Part Number
M0516LAN
Description
IC MCU 32BIT 64KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro M051™r
Specifications of M0516LAN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M0516LAN
Manufacturer:
Nuvoton
Quantity:
177
Company:
Part Number:
M0516LAN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
M0516LAN
Manufacturer:
NUVOTON
Quantity:
20 000
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6.7.8
SPI Control and Status Register (SPI_CNTRL)
Register
SPI_CNTRL
VARCLK_EN
Bits
[31:24]
[23]
[22:21]
[20:19]
SPI Controller Registers Description
31
23
15
7
NuMicro M051
Descriptions
Reserved
VARCLK_EN
Reserved
REORDER
Offset
SPIx_BA+ 0x00
30
22
14
6
SP_CYCLE
Reserved
TX_BIT_LEN
29
21
13
5
R/W
R/W
Reserved
Variable Clock Enable (Master Only)
0 = The serial clock output frequency is fixed and decided only by the value of
DIVIDER.
1 = The serial clock output frequency is variable. The output frequency is
decided by the value of VARCLK, DIVIDER, and DIVIDER2.
Note that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must
be programmed as 0x10 (16 bits mode)
Reserved
Reorder Mode Select
00 = Disable both Byte Reorder and byte suspend functions.
01 = Enable Byte Reorder function and insert a byte suspend interval (2~17
serial clock cycles) among each byte. The setting of TX_BIT_LEN must be
™
Description
Control and Status Register
Series Technical Reference Manual
28
20
12
4
- 246 -
REORDER
Reserved
CLKP
27
19
11
3
Publication Release Date: Sep 14, 2010
TX_NEG
SLAVE
LSB
26
18
10
2
RX_NEG
25
17
IE
9
1
TX_NUM
Revision V1.2
Reset Value
0x0000_0004
GO_BUSY
24
16
IF
8
0
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