ATTINY13A-SUR Atmel, ATTINY13A-SUR Datasheet - Page 72
ATTINY13A-SUR
Manufacturer Part Number
ATTINY13A-SUR
Description
IC MCU AVR 1K FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-SUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
ATTINY13
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
4.5 V to 5.5 V
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
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ATtiny13A
Table 11-5.
Table 11-6
PWM mode.
Table 11-6.
Note:
Table 11-7
correct PWM mode.
Table 11-7.
Note:
• Bits 3:2 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13A and will always read as zero.
COM0B1
COM0B1
COM0B1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See
for more details.
pare Match is ignored, but the set or clear is done at TOP. See
page 67
shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase
shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to fast
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
COM0B0
COM0B0
COM0B0
for more details.
0
1
0
1
0
1
0
1
0
1
0
1
Description
Normal port operation, OC0B disconnected.
Toggle OC0B on Compare Match
Clear OC0B on Compare Match
Set OC0B on Compare Match
Description
Normal port operation, OC0B disconnected.
Reserved
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Description
Normal port operation, OC0B disconnected.
Reserved
Clear OC0B on Compare Match, set OC0B at TOP
Set OC0B on Compare Match, clear OC0B at TOP
(1)
(1)
“Phase Correct PWM Mode” on
“Fast PWM Mode” on page 65
8126E–AVR–07/10
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