ATTINY13A-SNR Atmel, ATTINY13A-SNR Datasheet - Page 66

• Manufacturer Part Number: ATTINY13A-SNR
• Description: IC MCU AVR 1KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY13A-SNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

66
ATtiny13A
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in
shown as a histogram for illustrating the single-slope operation. The diagram includes non-
inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes repre-
sent Compare Matches between OCR0x and TCNT0.
Figure 11-6. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Setting the COM0x[1:0] bits to two will produce a non-inverted PWM and an inverted PWM out-
put can be generated by setting the COM0x[1:0] to three: Setting the COM0A[1:0] bits to one
allows the AC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not
available for the OC0B pin (See
ible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x
and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result
TCNTn
OCn
OCn
Period
1
2
Figure 11-6 on page
3
Table 11-3 on page
f
OCnxPWM
4
66. The TCNT0 value is in the timing diagram
5
=
------------------
N 256
f
clk_I/O
71). The actual OC0x value will only be vis-
⋅
6
7
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
8126E–AVR–07/10