ATTINY40-MMH Atmel, ATTINY40-MMH Datasheet - Page 10
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ATTINY40-MMH
Manufacturer Part Number
ATTINY40-MMH
Description
IC MCU AVR 4KB FLASH 12MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY40-SU.pdf
(18 pages)
Specifications of ATTINY40-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VFQFN Exposed Pad
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, TWI, ISB
Number Of Programmable I/os
18
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
10
BCLR
SBI
CBI
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
DATA TRANSFER INSTRUCTIONS
MOV
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
LDS
ST
ST
ST
ST
ST
ST
ST
ST
ST
STS
IN
OUT
PUSH
POP
MCU CONTROL INSTRUCTIONS
BREAK
NOP
SLEEP
WDR
Mnemonics
ATtiny40
s
A, b
A, b
Rr, b
Rd, b
Rd, Rr
Rd, K
Rd, X
Rd, X+
Rd, - X
Rd, Y
Rd, Y+
Rd, - Y
Rd, Z
Rd, Z+
Rd, -Z
Rd, k
X, Rr
X+, Rr
- X, Rr
Y, Rr
Y+, Rr
- Y, Rr
Z, Rr
Z+, Rr
-Z, Rr
k, Rr
Rd, A
A, Rr
Rr
Rd
Operands
Flag Clear
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow.
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Copy Register
Load Immediate
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Store Direct from SRAM
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect
Store Indirect and Post-Increment.
Store Indirect and Pre-Decrement
Store Direct to SRAM
In from I/O Location
Out to I/O Location
Push Register on Stack
Pop Register from Stack
Break
No Operation
Sleep
Watchdog Reset
Description
SREG(s) ← 0
I/O(A, b) ← 1
I/O(A, b) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
C ← 0
N ← 1
N ← 0
Z ← 1
Z ← 0
I ← 1
I ← 0
S ← 1
S ← 0
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
Rd ← Rr
Rd ← K
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Z)
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (k)
(X) ← Rr
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(k) ← Rr
Rd ← I/O (A)
STACK ← Rr
Rd ← STACK
(see specific descr. for Break)
(see specific descr. for Sleep)
(see specific descr. for WDR)
I/O (A) ← Rr
Operation
SREG(s)
None
None
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Flags
8263AS–AVR–08/10
#Clocks
1/2
2/3
1/2
2/3
1/2
2/3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
2
1
1
2
1
1
2
1
1
1
2
2
1
1
1
1