MC9S08JE64VLH Freescale Semiconductor, MC9S08JE64VLH Datasheet - Page 35
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MC9S08JE64VLH
Manufacturer Part Number
MC9S08JE64VLH
Description
IC MCU 8BIT 64K FLASH 64LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08JE128CMB.pdf
(44 pages)
Specifications of MC9S08JE64VLH
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
S08JE
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
12 KB
Maximum Clock Frequency
48 MHz
Operating Supply Voltage
- 0.3 V to + 3.8 V
Maximum Operating Temperature
+ 105 C
3rd Party Development Tools
EWS08
Development Tools By Supplier
TWR-SER, TWR-ELEV, TWR-MCF51JE-KIT, TWR-S08JE128-KIT, TWR-LCD
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08JE64VLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
2.12
Table 21
Freescale Semiconductor
1
2
3
4
No.
Numbers in this column identify elements in
All timing is shown with respect to 20% V
assumes slew rate control disabled and high drive strength enabled for SPI output pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
and
10
11
12
13
1
2
3
4
5
6
7
8
9
SPI Characteristics
1
Figure 11
Operating frequency
SPSCK period
Slave MISO disable time
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time
Fall time
through
Characteristic
Figure 14
3
4
describe the timing requirements for the SPI system.
2
Preliminary — Subject to Change
Master
Master
Master
Master
Master
Master
Master
Master
Master
Output
Output
DD
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Input
Input
Table 21. SPI Timing
Figure 11
and 70% V
t
Symbol
WSPSCK
t
SPSCK
t
t
Lead
t
t
t
t
t
t
f
Lag
t
t
t
HO
RO
t
SU
SU
dis
FO
through
op
t
t
HI
HI
RI
FI
a
v
DD
, unless noted; 100 pF load on all SPI pins. All timing
Figure
f
t
t
Bus
cyc
cyc
Min
1/2
1/2
15
15
25
—
—
—
—
—
—
—
—
/2048
0
2
4
1
1
0
0
0
14.
– 30
– 30
Preliminary Electrical Characteristics
1024 t
t
t
cyc
cyc
f
f
2048
Max
Bus
Bus
25
25
25
25
—
—
—
—
—
—
—
—
—
—
—
—
1
1
– 25
– 25
/2
/4
cyc
t
t
SPSCK
SPSCK
Unit
t
t
t
t
t
t
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc
C
D
D
D
D
D
D
D
D
D
D
D
D
D
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