MCF51JE256VMB Freescale Semiconductor, MCF51JE256VMB Datasheet - Page 18
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MCF51JE256VMB
Manufacturer Part Number
MCF51JE256VMB
Description
IC MCU 256K COLDF 81-PBGA
Manufacturer
Freescale Semiconductor
Series
MCF51JEr
Datasheet
1.TWR-MCF51JE.pdf
(50 pages)
Specifications of MCF51JE256VMB
Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI, USB OTG
Peripherals
LVD, PWM, WDT
Number Of I /o
48
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
81-LBGA
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, SCI, I2C
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Package
81MAPBGA
Device Core
ColdFire
Family Name
MCF51JE
Maximum Speed
50.33 MHz
On-chip Adc
8-chx12-bit
On-chip Dac
1-chx12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF51JE256VMB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Preliminary Electrical Characteristics
Solving
where K is a constant pertaining to the particular part. K can be determined from
P
solving
3.4
Although damage from static discharge is much less common on these devices than on early CMOS
circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification
tests are performed to ensure that these devices can withstand exposure to reasonable levels of static
without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade
Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the
device specification requirements. Complete dc parametric and functional testing is performed per the
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
1-1
D
(at equilibrium) for a known T
#
1
2
3
4
Equation 1
Human Body
Machine
Latch-up
Equation 1
ESD Protection Characteristics
Human Body Model (HBM)
Machine Model (MM)
Charge Device Model (CDM)
Latch-up Current at T
Model
and
and
Series Resistance
Storage Capacitance
Number of Pulse per pin
Series Resistance
Storage Capacitance
Number of Pulse per pin
Minimum input voltage limit
Maximum input voltage limit
Equation 2
Equation 2
Table 8. ESD and Latch-Up Protection Characteristics
A
Rating
= 125°C
Table 7. ESD and Latch-up Test Conditions
K = P
A
iteratively for any value of T
. Using this value of K, the values of P
for K gives:
Preliminary — Subject to Change
D
P
Description
× (T
D
= K ÷ (T
A
+ 273°C) + θ
J
+ 273°C)
Symbol
JA
V
V
V
I
HBM
CDM
LAT
MM
× (P
D
A
)
.
2
±2000
±200
±500
±100
Min
Symbol
R1
R1
—
—
—
—
C
C
D
and T
Equation 3
Max
—
—
—
—
J
Value
1500
–2.5
100
200
7.5
can be obtained by
Freescale Semiconductor
3
0
3
Unit
mA
V
V
V
by measuring
Unit
pF
pF
—
—
Ω
Ω
V
V
C
T
T
T
T
Eqn. 2
Eqn. 3