PK60X256VMD100 Freescale Semiconductor, PK60X256VMD100 Datasheet - Page 58

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PK60X256VMD100

Manufacturer Part Number
PK60X256VMD100
Description
IC ARM CORTEX MCU 256K 144-MAP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Datasheets

Specifications of PK60X256VMD100

Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
Peripherals
DMA, I²S, LVD, POR, PWM, WDT
Number Of I /o
100
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 33x16b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
Kinetis
Core
ARM Cortex M4
Data Ram Size
64 KB
Interface Type
UART, SPI, I2C, I2S, CAN
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
100
Operating Supply Voltage
1.71 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PK60X256VMD100
Manufacturer:
FSL
Quantity:
10
Part Number:
PK60X256VMD100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Peripheral operating requirements and behaviors
6.8.1.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
58
RMII1
RMII2
RMII3
RMII4
RMII7
RMII8
Num
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
RMII_CLK pulse width low
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
RMII_CLK to TXD[1:0], TXEN invalid
RMII_CLK to TXD[1:0], TXEN valid
Description
TXCLK (input)
TXD[n:0]
TXEN
TXER
RXCLK (input)
RXD[n:0]
RXDV
RXER
Table 39. RMII signal switching specifications
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Figure 22. MII transmit signal timing diagram
Figure 23. MII receive signal timing diagram
MII8
Preliminary
MII2
MII3
Valid data
Valid data
Valid data
MII6
Valid data
Valid data
Valid data
MII1
MII4
MII5
MII7
35%
35%
Min.
4
2
4
Freescale Semiconductor, Inc.
Max.
65%
65%
50
15
RMII_CLK
RMII_CLK
period
period
MHz
Unit
ns
ns
ns
ns

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