MCIMX515CJM6CR2 Freescale Semiconductor, MCIMX515CJM6CR2 Datasheet - Page 88

• Manufacturer Part Number: MCIMX515CJM6CR2
• Description: IC MPU I.MX51 529MABGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX515CJM6CR2

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Electrical Characteristics
4.7.8.4
The IPU Display Interface supports two kinds of display’s accesses: synchronous and asynchronous. There
are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.
4.7.8.4.1
The synchronous control is a signal that changes its value as a function either of a system or of an external
clock. This control has a permanent period and a permanent wave form.
There are special physical outputs to provide synchronous controls:
The IPU has a system of internal binding counters for internal events (like HSYNC/VSYCN and so on)
calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control
starts from the local start point with predefined UP and DOWN values to calculate control’s changing
points with half DI_CLK resolution. A full description of the counters system is in the IPU chapter of the
i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM).
4.7.8.4.2
The asynchronous control is a data oriented signal that changes its a value with an output data according
to an additional internal flags coming with the data.
There are special physical outputs to provide asynchronous controls, as follows:
4.7.8.5
4.7.8.5.1
The IPU uses four control signals and data to operate a standard synchronous interface:
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The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display
(component, pixel) clock for a display.
The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide
HSYNC, VSYNC, DRDY or any else independent signal to a display.
The ipp_d0_cs and ipp_d1_cspins are dedicated to provide chip select signals to two displays
The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide
WR. RD, RS or any else data oriented signal to display.
IPP_DISP_CLK—Clock to display
HSYNC—Horizontal synchronization
IPU Display Interface Timing
Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
Synchronous Controls
Asynchronous Controls
IPU Display Operating Signals
The IPU has independent signal generators for asynchronous signals
toggling. When a DI decides to put a new asynchronous data in the bus, a
new internal start (local start point) is generated. The signals generators
calculate predefined UP and DOWN values to change pins states with half
DI_CLK resolution.
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
NOTE
Freescale Semiconductor