CLC030VEC National Semiconductor, CLC030VEC Datasheet - Page 20

• Manufacturer Part Number: CLC030VEC
• Description: IC SERIALIZER VIDEO DGTL 64-TQFP
• Manufacturer: National Semiconductor

Specifications of CLC030VEC

• Function: Serializer
• Data Rate: 1.485Gbps
• Input Type: CMOS
• Output Type: CMOS
• Number Of Inputs: 7
• Number Of Outputs: 7
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CLC030VEC

www.national.com
Device Operation
FORMAT REGISTERS 0 (Addresses 0Bh)
The CLC030 may be set to process a single video format by
writing the appropriate data into the FORMAT 0 register. The
Format Set[4:0] bits confine the CLC030 to recognize and
process only one of the fourteen specified types of standard
or high definition formats. When the CLC030 is set to pro-
cess a single format, it will not recognize and therefore will
not process other formats that it is capable of recognizing.
The Format Set[4:0] bits may not be used to confine device
operation to a range of standards. For normal operating
situations, it is recommended that the CLC030 be operated
in automatic format detection mode, i.e. that the Format 0
register be set to 00h.
The available formats and codes are detailed in Table 4.
Generally speaking, the Format Set[4:0] codes indicate or
group the formats as follows: Format Set[4] is set for the HD
formats and reset for the SD formats. Format Set[3] when
FORMAT REGISTER 1 (Address 0Ch)
The CLC030 can automatically determine the format of the
incoming parallel data. The result of this operation is stored
in the FORMAT 1 register. The Format[4:0] bits identify
which of the many possible video data standards that the
CLC030 can process is being received. These format codes
follow the same arrangement as for the Format Set[4:0]
bits. These formats and codes are given in Table 4. Bit
Format[4] when set indicates that HD data is being pro-
cessed. When reset, SD data is indicated. Format[3] when
set indicates that PAL data is being processed. When reset
NTSC data is being processed. Format[2:0] correspond
with one of the sub-standards given in the table.
The H, V, and F bits register correspond to input TRS data
bits 6, 7 and 8, respectively. The meaning and function of
this data is the same for both standard definition (SMPTE
125M) and high definition (SMPTE 292M luminance and
[4,3,2,1,0]
Format
00001
00010
00011
01001
01010
01011
10001
10010
10011
11001
11010
10100
11100
11101
Code
SDTV, 54
SDTV, 36
SDTV, 27
SDTV, 54
SDTV, 36
SDTV, 27
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
Format
SMPTE 344M
SMPTE 267M
SMPTE 125M
ITU-R BT
601.5
ITU-R BT
601.5
ITU-R BT
601.5
SMPTE 260M
SMPTE 274M
SMPTE 274M
SMPTE 274M
SMPTE 274M
SMPTE 295M
SMPTE 274M
SMPTE 296M
Specification
(Continued)
TABLE 4. Video Raster Format Parameters
Frame
Rate
30P
25P
24P
60P
60I
60I
60I
50I
50I
50I
30I
30I
25I
25I
20
set indicates that PAL data is being processed. When reset
NTSC data is being processed. Format Set[2:0] correspond
to one of the sub-standards given in the table. Note that the
CLC030 makes no distinction in formats resulting from the
processing of data at 74.25MHz or 74.176MHz.
The HD Only bit when set to a logic-1 locks the CLC030 into
the high definition data range and frequency. In systems
designed to handle only high definition signals, enabling HD
Only reduces the time required for the CLC030 to establish
frequency lock and determine the HD format being pro-
cessed.
The SD Only bit when set to a logic-1 locks the CLC030 into
the standard definition data ranges and frequencies. In sys-
tems designed to handle only standard definition signals,
enabling SD Only reduces the time required for the CLC030
to establish frequency lock and determine the format being
processed. When SD Only and HD Only are set to logic-0,
the device operates in SD/HD mode.
color difference) video data. Polarity is logic-1 equals HIGH-
true. These bits are registered for the duration of the appli-
cable field.
TEST 0 REGISTER (Address 0Dh)
The Test Pattern Select bits determine which test pattern is
output when the Test Pattern Generator (TPG) mode or the
Built-in Self-Test (BIST) mode is enabled. Table 5 gives the
codes corresponding to the various test patterns. All HD
color bars test patterns are BIST data. Standard Definition
BIST test patterns are: NTSC, 27MHz, 4x3 color Bars and
PAL, 27MHz, 4x3 PLL Pathological.
The TPG Enable bit when set to a logic-1 enables the Test
Pattern Generator function and built-in self-test (BIST). This
bit is mapped to I/O port bit 7 in the default condition. Note
that the input pulldown on the I/O port bit has the effect of
overriding the logic level of data being written into the regis-
ter via the ancillary/Control Data Port. In cases where it is
desired to control the state of TPG Enable through the
Lines
1125
1125
1125
1125
1125
1250
1125
525
525
525
625
625
625
750
Active Lines
507/487
507/487
507/487
1035
1080
1080
1080
1080
1080
1080
577
577
577
720
Samples
3432
2288
1716
3456
2304
1728
2200
2200
2200
2640
2640
2376
2750
1650
Samples
Active
2880
1920
1440
1920
1920
1920
1920
1920
1280
2880
1920
1440
1920
1920