LM2512SM/NOPB National Semiconductor, LM2512SM/NOPB Datasheet - Page 3

• Manufacturer Part Number: LM2512SM/NOPB
• Description: IC SERIALIZER 24BIT RGB 49-UFBGA
• Manufacturer: National Semiconductor
• Series: LMr

Specifications of LM2512SM/NOPB

• Function: Serializer
• Data Rate: 468Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 21
• Number Of Outputs: 3
• Voltage - Supply: 1.6 V ~ 3 V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 49-UFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM2512SM

MPL SERIAL BUS PINS
SPI INTERFACE and CONFIGURATION PINS
VIDEO INTERFACE PINS
POWER/GROUND PINS
Pin Descriptions
Note:
I = Input, O = Output, IO = Input/Output. Do not float input pins.
SPI_SDA/HS
SPI_SDA/HS
Pin Name
SPI_CSX
SPI_SCL
MD[2:0]
G[7:0]
RES1
PCLK
R[7:0]
B[7:0]
V
V
V
V
PD*
V
V
MC
TM
NC
DE
VS
DDIO
SSIO
DDA
SSA
DD
SS
of Pins
No.
24
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
4
201728 Version 5 Revision 1
I/O, Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
O, MPL
O, MPL
Ground
Ground
Ground
Power
Power
Power
IO,
NA
IO,
I,
I,
I,
I,
I,
I,
I,
I,
I
MPL Data Line Driver
MPL Clock Line Driver
SPI_Chip Select Input
SPI port is enabled when: SPI_CSX is Low, PD* is High, and PCLK is static.
SPI_Clock Input
Multi-function Pin:
If SPI_CSX is Low, this is the SPI_SDA IO signal. Default is Input. Pin will be an
output for a SPI Read transaction.
See HS description below also.
Power Down Mode Input
SER is in sleep mode when PD* = Low, SER is enabled when PD* = High
In PD*=L - Sleep mode: SPI interface is OFF, Register settings are RESET, and
LUT data is retained.
Reserved 1 - Tie High (V
Test Mode
L = Normal Mode, tie to GND
H = Test Mode (Reserved)
Not Connected - Leave Open; only on SLH49A package..
Pixel Clock Input
Video Signals are latched on the RISING edge.
RGB Data Bus Inputs – Bit 7 is the MSB.
Vertical Sync. Input
This signal is used as a frame start for the Dither block and is required. The
VS signal is serialized unmodified.
Multi-function Pin:
Horizontal Sync. Input (when SPI_CSX = High)
See SPI_SDA description above also.
Data Enable Input
Power Supply Pin for the PLL (SER) and MPL Interface.
1.6V to 2.0V
Ground Pin for the PLL (SER) and MPL Interface.
Power Supply Pin for the digital core.
1.6V to 2.0V
Ground Pin for the digital core. For SNA40A package, this is the large center pad.
Power Supply Pin for the parallel interface I/Os.
1.6V to 3.0V
Ground Pin for the parallel interface I/Os. For SNA40A package, this is the large
center pad.
Print Date/Time: 2010/01/20 21:11:52
3
DDIO
) only available on SLH49A package
RGB Serializer
Description
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