CP2112-F01-GM Silicon Laboratories Inc, CP2112-F01-GM Datasheet
CP2112-F01-GM
Specifications of CP2112-F01-GM
Related parts for CP2112-F01-GM
CP2112-F01-GM Summary of contents
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... Supply Voltage Self-powered: 3.0 to 3.6 V USB bus powered: 4.0 to 5.25 V I/O voltage: 1 Ordering Part Number CP2112-F01-GM Package RoHS-compliant 24-pin QFN ( mm) Temperature Range: –40 to +85 °C CP2112 48 MHz Oscillator Peripheral ...
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... CP2112 2 Rev. 1.0 ...
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... QFN-24 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. USB Function Controller and Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. System Management Bus (SMBus) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1. SMBus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2. SMBus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3. CP2112 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1. GPIO.0-1—Transmit and Receive Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2. GPIO.7—Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8. One-Time Programmable ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 ...
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... The configurable options include the clock speed, read/write timeouts, retry counter timeout, SCL low timeouts, and a 7-bit device address. The CP2112 will only ACK the 7-bit device address assigned to it but will not respond to any read/write requests. External pull-up resistors are needed for the SCL and SDA signals. ...
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... The USB pull-up supply current values are calculated values based on USB specifications. Conditions V > 2 < 2 and GND IO Conditions ) Normal Operation; V Enabled REG Suspended; V Enabled REG Rev. 1.0 CP2112 Min Typ Max Units –55 — 125 °C –65 — 150 °C –0.3 — 5.8 V –0.3 — 3.6 – ...
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... Typ Max 0. — — IO — — 0.6 15 — — Min Typ Max 3.0 — 5.25 3.3 3.45 3.6 2.5 — — — — 120 CP2112 . Min Typ Max * Output x Output Output x 0.985 1.015 — 10 — — 10 — µA µA V Units V V µs ...
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... GPIO.7 12* D I/O CLK D Out *Note: Pins can be left unconnected when not in use. Table 7. CP2112 Pin Definitions Description Power Supply Voltage Input. Voltage Regulator Output. See Section 9. Ground. Must be tied to ground. Device Reset. Open-drain output of internal POR or V nal source can initiate a system reset by driving this pin low for the time specified in Table 4 ...
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... Pins can be left unconnected when not in use. 8 Description This pin is logic high when the CP2112 is in the USB Suspend state. This pin is logic low when the CP2112 is in the USB Suspend state. No connect This pin should be left unconnected of tied to V Rev. 1.0 ...
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... SDA 1 GND CP2112-GM Top View D- 4 VIO 5 GND (optional) VDD 6 Figure 2. QFN-24 Pinout Diagram (Top View) Rev. 1.0 CP2112 SUSPEND 16 VPP 15 GPIO.4 14 GPIO.5 13 GPIO.6 9 ...
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... CP2112 4. QFN-24 Package Specifications Table 8. QFN-24 Package Dimensions Dimension Min A 0.70 A1 0.00 b 0.18 D 4.00 BSC. D2 2.55 e 0.50 BSC. E 4.00 BSC. E2 2.55 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for custom features D2, E2 and L which are toleranced per supplier designation ...
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... A 2x2 array of 1. 1.10 mm openings on a 1.30 mm pitch should be used for the center pad. Card Assembly 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components. Dimension Min X2 2.70 Y1 0.65 Y2 2.70 Rev. 1.0 CP2112 Max 2.80 0.75 2.80 11 ...
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... The CP2112 operates as an SMBus master; however, it has an SMBus slave address that is configurable. The CP2112 will only ACK this address and will not respond to any read or write requests. If the least significant bit of the address is set, the device will ignore it. ...
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... CP2112 is a master device, the CP2112 will ACK this address but will not respond to any read or write requests. If the least significant bit is set, the CP2112 will ignore it. If auto read send is set to 0x01, the CP2112 will return the results of a read automatically. If this is set to 0x00, the device will wait for a “data read response” request to respond to data. ...
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... CP2112 7. GPIO Pins The CP2112 supports 8 user-configurable GPIO pins. Each of these GPIO pins are usable as inputs, open-drain outputs, or push-pull outputs. Three of these GPIO pins also have alternate functions which are listed in Table 10. Table 10. GPIO Pin Alternate Functions By default, all of the GPIO pins are configured as a GPIO input. The pins must be configured each time the device is reset ...
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... A vendor ID can be obtained from www.usb.org, or Silicon Labs can provide a free PID for the OEM product that can be used with the Silicon Labs VID. Customizing the serial string for each individual device is also recommended if the OEM application is one in which it is possible for multiple CP2112-based devices to be connected to the same PC. ...
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... CP2112 9. Voltage Regulator The CP2112 includes an on-chip 5.0 to 3.45 V voltage regulator. This allows the CP2112 to be configured as either a USB bus-powered device or a USB self-powered device. A typical connection diagram of the device in a bus- powered application using the regulator is shown in Figure 8. When enabled, the voltage regulator output appears on the V pin and can be used to power external devices ...
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... If programming the configuration ROM via USB, add a 4.7 F capacitor between VPP and ground. During a programming operation, do not connect the VPP pin to other circuitry, and ensure that VDD is at least 3.3 V. Figure 9. Typical Self-Powered Connection Diagram (Regulator Bypass) pin, the CP2112 can function as a USB self-powered DD CP2112 VIO ...
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... The CP2112 is a USB Human Interface Device (HID), and, since most operating systems include native drivers, custom drivers do not need to be installed. Because the CP2112 does not fit a standard HID device type, such as a keyboard or mouse, any CP2112 PC application needs to use the CP2112’s HID specification to communicate with the device. The low-level HID specification for the CP2112 is provided in “ ...
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... OCUMENT HANGE IST Revision 0.1 to Revision 0.5 Updated Table 3 on page 6. Updated Table 4 on page 6. Updated Table 5 on page 6. Updated Table 11 on page 15. Revision 0.5 to Revision1.0 Removed preliminary language. Rev. 1.0 CP2112 19 ...
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... CP2112 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...