73S8009C-32IM/F Maxim Integrated Products, 73S8009C-32IM/F Datasheet
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73S8009C-32IM/F
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73S8009C-32IM/F Summary of contents
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... The 73S8009C can operate from a single 2 6.5 V source supply combination of battery power (4 6.5 V) and USB power (4 5.5 V). The 73S8009C supports and 1.8 V smart cards. The smart card signals for RST, CLK, IO, and auxiliary signals AUX1 and AUX2 are level-shifted to the selected V ...
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... Data Sheet FEATURES • Smart card Interface: • Complies with ISO-7816-3 and EMV 4.1 and derivative standards • A DC-DC Converter provides 1.8 V/3 V the card from a wide range of external power supply inputs • Provides the card • ISO-7816-3 Card emergency deactivation sequencer • ...
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... VOLTAGE bias currents REFERENCE VCC FAULT VPC FAULT VCC OK VCC = 5 VCC = 3 POWER DOWN ON/OFF 1.5MHz R-C SMART CARD I/O BUFFERS AND SIGNAL LOGIC 28 GND Pin numbers reference the QFN32 package. Figure 1: 73S8009C Block Diagram DS_8009C_025 VBAT VBUS VPC 27 LIN SWITCH/LDO 17 GND ...
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... Digital Signals Characteristics ............................................................................................... 14 2.5 DC Characteristics ................................................................................................................ 15 2.6 Voltage / Temperature Fault Detection Circuits ...................................................................... 15 2.7 Thermal Characteristics ........................................................................................................ 15 3 Applications Information ............................................................................................................. 16 3.1 Example 73S8009C Schematics ........................................................................................... 16 3.2 Power Supply and Converter ................................................................................................. 18 3.3 Interface Function - ON/OFF Modes ...................................................................................... 18 3.4 System Controller Interface ................................................................................................... 20 3.5 Card Power Supply and Voltage Supervision......................................................................... 20 3.6 Activation and De-activation Sequence ...
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... DS_8009C_025 Figures Figure 1: 73S8009C Block Diagram ......................................................................................................... 3 Figure 2: 73S8009C 32-Pin QFN Pinout .................................................................................................. 6 Figure 3: Typical 73S8009C Application Schematic ............................................................................... 17 Figure 4: 73S8009C Logical Block Diagram ........................................................................................... 19 Figure 5: Activation Sequence ............................................................................................................... 21 Figure 6: Deactivation Sequence ........................................................................................................... 22 Figure 7: OFF Activity ............................................................................................................................ 22 Figure 8: CS Timing Definitions .............................................................................................................. 23 Figure 9: I/O and I/OUC State Diagram .................................................................................................. 24 Figure 10: I/O – I/OUC Delays - Timing Diagram .................................................................................... 25 Figure 11: On_Off Pin ............................................................................................................................ 26 Figure 12: Open Drain type – ...
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... Data Sheet 1 Pinout The 73S8009C is supplied as a 32-pin QFN package. 1 I/OUC AUX1UC 2 AUX2UC 3 4 CMDVCC5 5 CMDVCC3 RSTIN 6 CLKIN 7 RDY 8 Figure 2: 73S8009C 32-Pin QFN Pinout 6 TERIDIAN 73S8009C DS_8009C_025 24 ON_OFF 23 VBUS I AUX1 AUX2 20 VCC 19 18 RST GND 17 Rev. 1.5 ...
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... Power Supply and Ground VDD 29 PSO VPC 26 PSI VBAT 25 Rev. 1.5 Table 1: 73S8009C Pin Definitions Equivalent Circuit Figure 16 Card I/O: Data signal to/from card. Includes a pull-up resistor to V CC. Figure 16 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V Figure 16 AUX2: Auxiliary data signal to/from card. Includes a ...
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... CMDVCC% and CMDVCC#. Figure 18 Reset Input: This signal is the reset command to the card. Figure 12 Signal to controller indicating the 73S8009C is ready because V is above the required value after CC CMDVCC% and/or CMDVCC# is asserted low kΩ pull-up resistor to V disabled in Power down state and CS=0 modes. ...
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... OFF_REQ/OFF_ACK handshake. Figure 19 Digital output. Request to the host system controller to turn the 73S8009C off. If ON_OFF switch is closed (to ground) for de-bounce duration and circuit is “on,” OFF_REQ will go high (Request to turn OFF). Connected to OFF_ACK via 100 kΩ internal resistor. ...
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... Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8009C. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. The smart card interface pins are protected against short circuits ground, and each other ...
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... PC Supply Voltage V BUS Supply Voltage V BAT Ambient operating temperature 2.3 Smart Card Interface Requirements Table 4 lists the 73S8009C Smart Card interface requirements. Table 4: DC Smart Card Interface Requirements Symbol Parameter Card Power Supply (V ) Regulator CC General Conditions: -40C < 85C, 2.7 V < V Card supply voltage ...
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... Data Sheet V Vcc ready voltage (RDY rdy = 1) V RDY = 0 CCF (V voltage supervisor CC threshold) C External filter cap for V VPC Cvp External filter cap for VP External filter capacitor GND VDD filter capacitor VDD Ivpcoff VPC supply current for Vcc operation, Vcc rising 3 V operation, Vcc rising 1 ...
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... V CC For output high, shorted to ground through 33 Ω For I/O, AUX1, AUX2 80pF, 10% to 90%. L For I/OUC, AUX1UC, AUX2UC, CL=50Pf, 10% to 90%. Output stable for >200ns Edge from master to slave, measured at 50% 73S8009C Data Sheet Min Nom Max – – 0. +0.1 ...
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... Output rise time, fall time R F δ Duty cycle for CLK 2.4 Digital Signals Characteristics Table 5 lists the 73S8009C digital signals characteristics. Table 5: Digital Signals Characteristics Symbol Parameter Digital I/O (except for I/OUC, AUX1UC, AUX2UC; see Smart Card Interface Requirements for those specifications) V ...
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... Vpc = 2.7V, V off Vpc = 3.3V, V off Vpc = 5.0V, V off OFF mode V =3 Condition Table 8: Thermal Characteristics Condition 73S8009C Data Sheet Min Nom Max Unit 3.0 3.3 3.6 V – – – 1.7 – mA – 1.1 – mA – 0.7 – mA µA – ...
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... The documents listed in Related Documentation provide more detailed information. 3.1 Example 73S8009C Schematics Figure 3 shows a typical application schematic for the implementation of the 73S8009C with a main system switch. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information. ...
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... VCC RSTIN 7 CLKIN RST 8 RDY GND 73S80009C 32 QFN VDD See NOTE 4 4.7µF Card detection switch is and BAT C2 normally closed Figure 3: Typical 73S8009C Application Schematic 73S8009C Data Sheet C3 C6 10µF 0.1µF See NOTE 1 VBUS Pushbutton Switch 24 23 SW1 27pF See ...
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... OFF_REQ = 1. The default state upon application of power is the “OFF” state unless power is supplied to the V time, the controller may assert OFF_ACK and the 73S8009C will go into the “OFF” state (when V not present.) ...
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... OFF_ACK V PC 10µF 0.1µF 10uH CMDVCC# CMDVCC% PRES PRES Supply/ Control I/OUC Logic RSTIN CLKIN AUX1UC AUX2UC Figure 4: 73S8009C Logical Block Diagram Rev. 1.5 Linear 3.5V REF Converter V P Analog Mux V Regulator CC SHUTDOWN Card 3.3V Regulator GND V P 4.7µF ...
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... The smart card pass through signals are enabled when the RDY conditions are met. 3.5 Card Power Supply and Voltage Supervision The 73S8009C smart card interface IC incorporates an LDO voltage regulator for the card power supply conversion uses an internal LDO). The voltage output is controlled by the digital input ...
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... The host controller is fully responsible for the activation sequencing of the smart card signals CLK, RST, I/O, AUX1 and AUX2. All these signals are held low by the 73S8009C when the card is in the de- activated state. Upon card activation (the fall of CMDVCC (#/%)), all the signals are held low by the 73S8009C until RDY goes high ...
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... Data Sheet CMDVCC RST CLK I/O VCC_ON VCC t1 OFF and Fault Detection 3.7 There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. ...
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... With regard to de-activation, CS does not affect the operation of the fault sensing circuits and card sense input. CS OFF, I/OUC, AUX1UC, AUX2UC CONTROL SIGNALS Rev. 1 HI-Z STATE FUNCTIONAL Figure 8: CS Timing Definitions 73S8009C Data Sheet t DZ HI-Z STATE ...
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... Data Sheet 3.9 I/O Circuitry and Timing The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the activation sequencer turns on the I/O reception state. See the section for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset ...
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... The delay between the I/O signals is shown in Figure 10. I/O I/OUC Delay from I/O to I/OUC: Delay from I/OUC to I/O: Figure 10: I/O – I/OUC Delays - Timing Diagram Rev. 1.5 t I/O_HL t I/O_LH t = 100ns I/O_HL t = 100ns I/OUC_HL 73S8009C Data Sheet t t I/OUC_HL I/OUC_LH t = 15ns I/O_LH t = 15ns I/OUC_LH 25 ...
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... Data Sheet 4 Equivalent Circuits This section provides illustrations of circuits equivalent to those described in the PIN Output Disable circuit Figure 12: Open Drain type – OFF and RDY PIN Figure 13: Power Input/Output Circuit, VDD, LIN, VPC, VCC 24K ESD Figure 11: On_Off Pin VDD ...
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... DS_8009C_025 From circuit Figure 14: Smart Card CLK Driver Circuit From circuit Figure 15: Smart Card RST Driver Circuit Rev. 1.5 73S8009C Data Sheet VCC VERY STRONG ESD PFET CLK PIN ESD VERY STRONG NFET VCC STRONG ESD PFET RST PIN ESD STRONG ...
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... Data Sheet From circuit To circuit Figure 16: Smart Card IO, AUX1, and AUX2 Interface Circuit From circuit To circuit Figure 17: Smart Card I/OUC, AUX1UC and AUX2UC Interface Circuit 28 VCC STRONG PFET 400ns DELAY STRONG NFET ESD VDD STRONG PFET 400ns DELAY STRONG NFET ...
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... The diodes represent ESD protection devices that will conduct current if forward biased. Rev. 1.5 VDD VERY WEAK PFET VERY WEAK NFET Figure 18: General Input Circuit VDD STRONG PFET STRONG NFET Ω. Ω. Ω. Ω. Figure 19: OFF_REQ Interface Circuit 73S8009C Data Sheet ESD PIN ESD ESD PIN ESD 100k ohm To OFF_ACK pad 29 ...
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... Data Sheet 5 Mechanical Drawings TOP VIEW 0.2 MIN. 0.35 / 0.45 Figure 20: 32-Pin QFN Package Dimensions 30 0.85 NOM. 2.5 3.0 / 3.75 0.18 / 0.3 1.5 / 1.875 0.25 0.5 BOTTOM VIEW DS_8009C_025 / 0.9MAX. 0.00 / 0.005 0.20 REF. SEATING PLANE SIDE VIEW CHAMFERED 0.30 ...
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... For more information about Teridian Semiconductor products or to check the availability of the 73S8009C, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices http://www.teridian.com. Rev. 1.5 73S8009C Data Sheet Order Number Packaging Mark 73S8009C-32IM/F 73S8009C-32IMR/F 73S8009C 73S8009C 31 ...
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... Data Sheet Revision History Revision Date 1.0 2/15/2007 First publication. 1.1 12/5/2007 Replaced 32QFN punched with SAWN. Updated 32QFN package mark. 1.2 1/21/2008 Changed the dimension of the bottom view 32-pin QFN package. 1.3 8/28/2009 Added Pin Current, LIN to Added Added a note to the end of ...