SI2707-A10-GM Silicon Laboratories Inc, SI2707-A10-GM Datasheet

Page 1

EMI M ITIGATING Features  Digital input Delta-Sigma PWM  Patent-pending EMI mitigation  AM radio band noise-free notch  GSM/iPhone friendly  Wideband PWM carrier spreading  Power stage slew rate control  Power stage feedback for PSR/THD 2x ...

Page 2

Si2704/05/06/07-A10 2 Rev. 0.6 ...

Page 3

T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

... Si2704/05/06/07-A10 8.1. 24-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2. 48-Pin eTQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9. Package Markings (Top Marks 9.1. Si2707 Top Mark (QFN 9.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.3. Si2707 Top Mark (eTQFP 9.4. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4 ...

Page 5

Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Power Output Supply Voltage Main Supply Voltage Interface (I/O) Supply Voltage Load Impedance Ambient Temperature Junction Temperature Case Delta from Junction 3 Delta from Junction to Ambient Notes: 1. All ...

Page 6

Si2704/05/06/07-A10 Table 3. DC Characteristics—Supplies and Interfaces (V = 2 1. Parameter Symbol Start Up Time T ONSB T ON_SLP T ON_PD Active Mode Quiescent I PQ Supply Current ...

Page 7

Table 4. DC Characteristics—Class D Amplifier (V = 2 1. Parameter Output Voltage Offset Total Drain-Source On-State Resistance (Total Bridge)* *Note: Excludes package bond wire resistance. Table 5. AC ...

Page 8

Si2704/05/06/07-A10 Table 5. AC Characteristics—Class D Amplifier (Continued 2 1. Power Supply Rejection Ratio Crosstalk 4 Efficiency Output Pulse Repetition Frequency Notes: 1. Measured at filter output. ...

Page 9

Figure 1. Digital Audio Timing Parameters Table 8. 2-Wire Control Interface Characteristics (V = 1. –20 to +85 °C, unless otherwise noted Parameter SCLK Frequency SCLK Low Time SCLK High Time SCLK Input ...

Page 10

Si2704/05/06/07-A10 Table 9. 2-Wire Control Interface Address Selection CLKO Startup Voltage (Pin Table 10. Reset Timing Characteristics (V = 1. -20 to +85 °C, unless otherwise noted Parameter CLKO Setup Time to RST↑ ...

Page 11

SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 3. 2-Wire Control Interface Read and Write Timing Parameters SCLK SDIO A6-A0, 0 (Write) START ADDRESS + R/W SDIO A6-A0, 1 (Read) START ADDRESS ...

Page 12

Si2704/05/06/07-A10 Table 11. Reference Clock and Crystal Characteristics (V = 2 1. Parameter Reference Clock, Pin XTLI 1 Supported Frequencies Frequency Tolerance 2 Jitter Tolerance High Level Input Voltage ...

Page 13

Typical Application Schematic VDD 2 0.1 uF VIO 1. XTLI X1 22 XTLO 20 RSTB 24 DFS 1 DCLK 2 DIN 4 SCLK 5 SDIO 6 CLKO SLEEP/MFP3 ...

Page 14

Si2704/05/06/07-A10 3. Typical System Configurations 2.7–3.6 V Supply Dock Dock I/F Stereo Line ADC In System MCU User I/F Figure 6. Basic PMP Dock System Configuration 2.7–3.6 V Supply Digital Media Controller Dock Radio Tuner Dock I/F Si473x-D Stereo Line ...

Page 15

XTLI Digital XTLO Midrange Media Amplifier Controler Si270x adress 0x36 System 2-Wire CLKO MCU XTLI Tweeter Amplifier Si270x Radio adress 0x94 Figure 8. Stereo 2-Way Speaker System Configuration ...

Page 16

Si2704/05/06/07-A10 4. Functional Description 2.7 – 3.6 V VDD Supply CLKO 1.62 – 3.6 V VIO Supply MFP System Control 2-Wire Control Figure 10. Functional Block Diagram The Si2704/05/06/07 EMI mitigating 2 Class D ...

Page 17

PWM Processing The Si270x is designed to operate using a bridge-tied-load (BTL) output configuration where both sides of the speaker are actively driven by the amplifier. 4.1.1. PWM Switching Rate Control The output PWM switching frequency can be programmed ...

Page 18

Si2704/05/06/07-A10 Figure 11. PWM CM Spectrum for Integer Mode PWM Figure 12. PWM CM Spectrum for Fractional Mode PWM 4.1.2.3. Spectral Spreading Spread mode PWM can be used to spread PWM common mode switching energy resulting in a peak energy ...

Page 19

The noise-free notch can be dynamically tuned during normal operation without adversely affecting the internal audio processing ...

Page 20

Si2704/05/06/07-A10 POWER_DOWN Sleep Mode 4.2.2. Standby Mode Standby Mode is a reduced power state where the register states are preserved and the 2-Wire interface is fully operational, allowing for new parameters and configuration settings to be programmed even though the ...

Page 21

Standby Mode so that the high power outputs are prevented from being enabled prior to the registers being configured. Any other command sent to the device is acknowledged on the bus but ignored by the device. This mode has the ...

Page 22

Si2704/05/06/07-A10 4.3.2. Output Mode Configuration (Si2705/07 only) The Si2705/07 can be programmed via 2-Wire or configured using the OUTSEL MFP to operate in three different output modes: 2.1 mode, 2.0 mode and aux out mode, with the 2.0 mode being ...

Page 23

Figure 16. Headphone Plug Detection Application Schematic 4.4. Clocking A low jitter on-chip PLL synchronizes to an external clock reference and generates all necessary internal clocks. Three options are available for the external reference: a crystal, a reference clock or ...

Page 24

Si2704/05/06/07-A10 2 4.5. Digital Audio I S Interface The Si270x receives digital audio data using its I an input or output while DIN is restricted to input only, and all three can be configured to operate in either master or ...

Page 25

INVERTED (IFALL = 1) DCLK (IFALL = 0) DCLK DFS I2S 0x00 1 DCLK DIN n n-1 MSB INVERTED (IFALL = 1) DCLK (IFALL = 0) DCLK DFS Left-Justified 0x03 DOUT n n-1 n-2 MSB Figure 18. Left-Justified Digital Audio ...

Page 26

... Digital Audio Processing (DAP) The Si270x implements programmable digital audio processing which features volume control, dynamic range compressor (DRC), and audio filtering such as tone control, parametric equalization, crossover, and de-emphasis. The three channel digital audio processing chain for the Si2707 is shown in Figure 20. 32.0 44.1kHz 48 ...

Page 27

Parametric Equalization (Si2706/07 only) The Si2706/07 includes 16 fully programmable parametric equalizer filters. Seven of these filters are implemented in each of the Left/Right main channels and the remaining two are used for the Aux Channel. The filters are ...

Page 28

Si2704/05/06/07-A10 4.6.3. De-Emphasis (Si2706/07 only) The Si2706/07 features a de-emphasis filtering option in order to be able to process recorded audio that for noise reasons has been subject to 50/15 µs pre-emphasis. The 50/15 µs filter implemented has corner frequencies ...

Page 29

Dynamic Range Compression (Si2706/07 only) The Si2706/07 features dynamic range compression (DRC) with programmable linear gain, compression threshold, compression ratio, look ahead time, attack rate, and release rate. DRC increases the net output power without clipping by decreasing the ...

Page 30

Si2704/05/06/07-A10 Figure 24. Time Domain Characteristics of the Audio Dynamic Range Controller 4.6.7. Hard Signal Limiter The device implements a hard limiter to avoid exceeding the maximum modulation rate of the amplifier. The hard limiter is always enabled. 4.6.8. DC ...

Page 31

Power Supply and Grounding Considerations Careful attention should be given to the power and ground routing to allow for optimal performance of the Si270x. The low voltage supplies, V and possible so that parasitic inductances are ...

Page 32

Si2704/05/06/07-A10 5. Commands and Properties Table 16 and Table 17 are the summary of commands and properties for the Si270x Class D Audio Amplifier device. Table 16. Class D Audio Amplifier Command Summary Number Name 0x01 POWER_UP 0x10 FUNC_INFO 0x12 ...

Page 33

Table 17. Class D Audio Amplifier Property Summary (Continued) Category Number Biquad 0x1901 CROSSOVER_FREQ Filter 0x2103 BASS_BOOST_CUT 0x2104 BASS_CORNER_FREQ 0x2105 TREBLE_BOOST_CUT 0x2106 TREBLE_CORNER_FREQ Volume 0x2201 VOLUME_MUTE 0x2202 VOLUME_MASTER 0x2203 VOLUME_BALANCE 0x2204 VOLUME_AUX_CHANNEL 0x2205 VOLUME_RAMP DRC 0x2301 DRC_CONFIG 0x2302 DRC_THRESHOLD 0x2303 ...

Page 34

Si2704/05/06/07-A10 6. Pin Descriptions 6.1. 24-Pin QFN Package Pin Number Name GND PAD GND 1 DCLK 2 DIN 3 VIO 4 SCLK 5 SDIO 6 CLKO 7 MFP3 8 AUXOL 9 AUXOR 10 MFP1 11 OUTSEL/MFP2 12 VPPR 13 OUTPR ...

Page 35

Package Pin Number Name 1, 10, 11, 12, 13, NC 14, 15, 16, 23, 24, 25, 36, 37, 38, 39, 45, 46, 47 DFS 3 DCLK 4 DIN 5 VIO 6, 20, 28, 33, 43 ...

Page 36

Si2704/05/06/07-A10 Table 19. Pin Descriptions (Continued) Pin Number Name 29 OUTNR 30 GNDR 31 GNDL 32 OUTNL 34 OUTPL 35 VPPL 40 RST 41 XTLO 42 XTLI 44 VDD 36 Function Right channel power stage “N” output. Right channel power ...

Page 37

... AM radio Si2706-A10-GM 2.0 EMI Mitigating Class D Power Amplifier with Si2706-A10-GQ 2.0 EMI Mitigating Class D Power Amplifier with Si2707-A10-GM 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio with EQ/DRC Si2707-A10-GQ 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio with EQ/DRC *Note: Add an “ ...

Page 38

Si2704/05/06/07-A10 8. Package Outline 8.1. 24-Pin QFN Package Figure 27 illustrates the package details for 24-pin QFN package option for the Si2704/05/06/07. Table 20 lists the values for the dimensions shown in the illustration.   Table 20. 24-Pin QFN Package ...

Page 39

Package Figure 28 illustrates the package details for 48-pin eTQFP package option for the Si2704/05/06/07. Table 21 lists the values for the dimensions shown in the illustration. Si2704/05/06/07-A10 Figure 28. 48-Pin eTQFP Rev. 0.6 39 ...

Page 40

Si2704/05/06/07-A10 Table 21. 48-Pin eTQFP Package Dimensions Dimension Min Nom A — — A1 0.05 — A2 0.95 1.00 b 0.17 0.22 c 0.09 — D 9.00 BSC D1 7.00 BSC D2 3.71 3.81 e 0.50 BSC Notes: 1. All ...

Page 41

... Package Markings (Top Marks) 9.1. Si2707 Top Mark (QFN) 9.2. Top Mark Explanation Mark Method YAG Laser Line 1 Marking Part Number Firmware Revision Line 2 Marking Die Revision TTTTT = Internal Code Line 3 Marking Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Work Week Si2704/05/06/07-A10 ...

Page 42

... Si2704/05/06/07-A10 9.3. Si2707 Top Mark (eTQFP) 9.4. Top Mark Explanation Mark Method YAG Laser Line 1 Marking Part Number Firmware Revision Line 2 Marking Die Revision TTTTT = Internal Code Line 3 Marking Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Work Week 42 Si2704 Si2705 Si2706 Si2707 10 = Firmware Revision 1 ...

Page 43

Additional Reference Resources  Si270x Evaluation Board User’s Guide  AN469: 270x Programming Guide  AN470: 270x Layout Guidelines  AN502: Si270x Class-D Amplifier—Analog Source Setup  AN503: Si270x Class-D Amplifier—Dynamic Range Compressor Use  AN504: Si270x Class-D Amplifier—Dynamic ...

Page 44

... Added note to "7. Ordering Guide" on page 37.  Added "9. Package Markings (Top Marks)" on page 41.  Added "9.3. Si2707 Top Mark (eTQFP)" on page 42. Revision 0.5 to Revision 0.6  Updated eTQFP pin assignments on pages 1 and 35.  Updated eTQFP pin descriptions in Table 19 on page 35.  ...

Page 45

N : OTES Si2704/05/06/07-A10 Rev. 0.6 45 ...

Page 46

... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...