LC4256ZE-P-EVN Lattice, LC4256ZE-P-EVN Datasheet - Page 5

• Manufacturer Part Number: LC4256ZE-P-EVN
• Description: Development Software ispMACH 4000ZE Pico Eval Board
• Manufacturer: Lattice
• Series: ispMACH®r
• Type: CPLDr

Specifications of LC4256ZE-P-EVN

• Tool Type: Development Software Kit
• Core Architecture: CPLD
• Silicon Manufacturer: Lattice Semiconductor
• Kit Contents: Evaluation Board, USB Connector Cable. Quick Start Guide
• Features: High-Side Current Sensor Circuits
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Contents: Board, Cable, Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LC4256ZE-5MN144C

Lattice Semiconductor
Product Term Allocator
The product term allocator assigns product terms from a cluster to either logic or control applications as required
by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-
ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated
with the cluster. Table 2 shows the available functions for each of the five product terms in the cluster.
Table 2. Individual PT Steering
Cluster Allocator
The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions
with more product terms. Table 3 shows which clusters can be steered to which macrocells. Used in this manner,
the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator
accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.
Table 3. Available Clusters for Each Macrocell
Wide Steering Logic
The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-
tor n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions
and allowing performance to be increased through a single GLB implementation. Table 4 shows the product term
chains.
Product Term
Macrocell
PT
PT
PT
PT
PT
M10
M11
M12
M13
M14
M15
n
n
n
n
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
n
+1
+2
+3
+4
Logic PT
Logic PT
Logic PT
Logic PT
Logic PT
Logic
C10
C11
C12
C13
C14
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
—
Single PT for XOR/OR
Individual Clock (PT Clock)
Individual Initialization or Individual Clock Enable (PT Initialization/CE)
Individual Initialization (PT Initialization)
Individual OE (PTOE)
5
C10
C11
C12
C13
C14
C15
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
Available Clusters
ispMACH 4000ZE Family Data Sheet
Control
C10
C11
C12
C13
C14
C15
C1
C2
C3
C4
C5
C6
C7
C8
C9
—
C10
C11
C12
C13
C14
C15
C2
C3
C4
C5
C6
C7
C8
C9
—
—