WM9711LGEFL/V Wolfson Microelectronics, WM9711LGEFL/V Datasheet - Page 54

• Manufacturer Part Number: WM9711LGEFL/V
• Description: Audio CODECs Stereo AC'97 CODEC with H/P
• Manufacturer: Wolfson Microelectronics

Specifications of WM9711LGEFL/V

• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Interface Type: AC97
• Resolution: 12 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN EP
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 3
• No. Of Input Channels: 9
• No. Of Output Channels: 4
• Adc / Dac Resolution: 12bit
• Adcs / Dacs Signal To Noise Ratio: 94dB
• Sampling Rate: 48kHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM9711L
w
1Ch
20h
22h
24h
* “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0.
ADDR
ADDR
ADDR
ADDR
Register 1Ch controls the recording gain.
Register 20h is a “general purpose” register as defined by the AC’97 specification. Only two bits are implemented in the
WM9711L.
Register 22h controls 3D stereo enhancement for the audio DACs.
Register 24h is for power management additional to the AC’97 specification. Note that the actual state of each circuit block
depends on both register 24h AND register 26h.
REG
REG
REG
REG
15
14
13:8
7
6
5:0
13
7
5
4
3:0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BIT
BIT
BIT
BIT
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
LABEL
RMU
GRL
RECVOLL
ZC
GRR
RECVOLR
3DE
LB
3DLC
3DUC
3DDEPTH
LABEL
LABEL
LABEL
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
DEFAULT
0 (OFF)
0 (OFF)
DEFAULT
1 (mute)
0 (standard)
000000 (0dB)
0 (OFF)
0 (standard)
000000 (0dB)
0 (low)
0 (high)
0000 (0%)
DEFAULT
DEFAULT
Disables Crystal Oscillator
Disables left audio DAC
Disables right audio DAC
Disables left audio ADC
Disables right audio ADC
Disables MICBIAS
Disables left headphone mixer
Disables right headphone mixer
Disables speaker mixer
Disables MONO_OUT buffer (pin 33) and phone mixer
Disables OUT3 buffer (pin 37)
Disables headphone buffers (HPOUTL/R)
Disables speaker outputs (LOUT2, ROUT2)
Disables Line Input PGA (left and right)
Disables Phone Input PGA
Disables Mic Input PGA (left and right)
Enables 3D enhancement
Enables loopback (i.e. feed ADC output data
directly into DAC)
Mutes audio ADC input
Selects gain range for PGA of left ADC. 0=0...+22.5dB in
1.5dB steps, 1=-17.25...+30dB in 0.75dB steps
Controls left ADC recording volume
Enables zero-cross detector
Selects gain range for PGA of left ADC. 0=0...+22.5dB in
1.5dB steps, 1=-17.25...+30dB in 0.75dB steps
Controls right ADC recording volume
Selects lower cut-off frequency
Selects upper cut-off frequency
Controls depth of 3D effect
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
Enhancement
Intel’s AC’97 Component
Specification, Revision 2.2, page 55
Audio DACs, 3D Stereo
PD Rev 4.3 August 2006
REFER TO
Production Data
Audio ADC,
Record Gain
Audio DACs,
3D Stereo
Enhancement
Power
Management
REFER TO
REFER TO
REFER TO
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