MAX98088EWY+T Maxim Integrated Products, MAX98088EWY+T Datasheet - Page 113

• Manufacturer Part Number: MAX98088EWY+T
• Description: Audio CODECs DUAL I2S CODEC AUDIO STEREO
• Manufacturer: Maxim Integrated Products

Specifications of MAX98088EWY+T

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Resolution: 24 bit
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: WLP-63
• Number Of Channels: 2
• Supply Current: 4.5 mA
• Thd Plus Noise: - 77 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
IC, the seven most significant bits are 0010000. Setting
the read/write bit to 1 (slave address = 0x21) configures
the IC for read mode. Setting the read/write bit to 0 (slave
address = 0x20) configures the ICs for write mode. The
address is the first byte of information sent to the IC after
the START condition.
The acknowledge bit (ACK) is a clocked 9th bit that the
IC uses to handshake receipt each byte of data when
in write mode (Figure 34). The IC pulls down SDA dur-
ing the entire master-generated 9th clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
Figure 36. Writing n-Bytes of Data to the ICs
Figure 34. Acknowledge
Figure 35. Writing One Byte of Data to the ICs
S
ACKNOWLEDGE FROM MAX98088/
S
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX98088/
SLAVE ADDRESS
MAX98089
R/W
O
SCL
SDA
A
CONDITION
MAX98089
ACKNOWLEDGE FROM MAX98088/
R/W
START
O
REGISTER ADDRESS
A
Slave Address
Acknowledge
MAX98089
1
with FlexSound Technology
ACKNOWLEDGE FROM MAX98088/
REGISTER ADDRESS
2
A
ACKNOWLEDGE FROM MAX98088/
B7 B6 B5 B4 B3 B2 B1 B0
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
is busy or if a system fault has occurred. In the event
of an unsuccessful data transfer, the bus master retries
communication. The master pulls down SDA during the
9th clock cycle to acknowledge receipt of data when
the IC is in read mode. An acknowledge is sent by the
master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the IC, followed by a
STOP condition.
A write to the IC includes transmission of a START condi-
tion, the slave address with the R/W bit set to 0, one byte
of data to configure the internal register address pointer,
one or more bytes of data, and a STOP condition. Figure
35 illustrates the proper frame format for writing one byte
of data to the IC. Figure 35 illustrates the frame format for
writing n-bytes of data to the IC.
NOT ACKNOWLEDGE
DATA BYTE 1
ACKNOWLEDGE
MAX98089
1 BYTE
8
ACKNOWLEDGMENT
Stereo Audio Codec
CLOCK PULSE FOR
MAX98089
A
9
B7
A
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
B6
ACKNOWLEDGE FROM MAX98088/
B5
ACKNOWLEDGE FROM MAX98088/
B7 B6 B5 B4 B3 B2 B1 B0
DATA BYTE
B4
1 BYTE
B3
DATA BYTE n
1 BYTE
B2
MAX98089
Write Data Format
B1
MAX98089
B0
A
A
P
P
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