CS48540-DQZ Cirrus Logic Inc, CS48540-DQZ Datasheet - Page 18

• Manufacturer Part Number: CS48540-DQZ
• Description: Audio DSPs High Perform. 32-Bit Audio Decoder DSP
• Manufacturer: Cirrus Logic Inc

Specifications of CS48540-DQZ

• Operating Supply Voltage: 1.8 V
• Mounting Style: SMD/SMT
• Package / Case: LQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS485xx Family Data Sheet
32-bit Audio Decoder DSP Family
5.15 Switching Characteristics — Digital Audio Output Port
18
DAO_MCLK period
DAO_MCLK duty cycle
DAO_SCLK period for Master or Slave mode
DAO_SCLK duty cycle for Master or Slave mode
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input
DAO_LRCLK delay from DAO_SCLK transition, respectively
DAO_SCLK delay from DAO_LRCLK transition, respectively
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition
DAO_LRCLK delay from DAO_SCLK transition, respectively
DAO_SCLK delay from DAO_LRCLK transition, respectively
1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce
3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
DAO_SCLK, DAO_LRCLK.
data is valid.
Master Mode (Output A1 Mode)
Slave Mode (Output A0 Mode)
Figure 8. Direct Stream Digital - Serial Audio Input Timing
Parameter
3
3
Copyright 2009 Cirrus Logic, Inc.
1
1,2
4
1
CONFIDENTIAL
3
3
3
3
Symbol
T
t
t
T
t
t
t
t
daomsck
t
daomstlr
daomlrts
daomdv
daosstlr
daoslrts
daomclk
daosdv
daosclk
-
-
Min
40
45
40
40
-
-
-
-
-
-
-
Max
55
60
19
10
15
30
15
8
8
-
-
DS734F3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%