MAX11200EEE+ Maxim Integrated Products, MAX11200EEE+ Datasheet
MAX11200EEE+
Specifications of MAX11200EEE+
Related parts for MAX11200EEE+
MAX11200EEE+ Summary of contents
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... S On-Demand Offset and Gain Self-Calibration and System Calibration S User-Programmable Offset and Gain Registers S -40°C to +85°C Operating Temperature Range S Q2kV ESD Protection S Lead(Pb)-Free and RoHS-Compliant QSOP Package PART MAX11200EEE+ MAX11210EEE+ +Denotes a lead(Pb)-free/RoHS-compliant package. 4-WIRE SPI, 16-PIN QSOP MAX11200 MAX11207 MAX11211 ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO ABSOLUTE MAXIMUM RATINGS Any Pin to GND ....................................................-0.3V to +3.9V AVDD to GND .......................................................-0.3V to +3.9V DVDD to GND ......................................................-0.3V to +3.9V Analog Inputs (AINP, AINN, REFP, REFN) to GND ............................................. -0.3V to ...
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Single-Channel, Ultra-Low-Power, ELECTRICAL CHARACTERISTICS (continued +3.6V +1.7V, V AVDD DVDD REFP unless otherwise noted. Typical values are at T PARAMETER SYMBOL Absolute Input Voltage DC Input Leakage AIN Dynamic Input Current REF Dynamic Input Current ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO ELECTRICAL CHARACTERISTICS (continued +3.6V +1.7V, V AVDD DVDD REFP unless otherwise noted. Typical values are at T PARAMETER SYMBOL POWER REQUIREMENTS Analog Supply V Digital Supply V Total Operating ...
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Single-Channel, Ultra-Low-Power +3.6V +1.8V, V AVDD DVDD REFP are +25NC.) A ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (NO BUFFERS ENABLED) 260 LINEF = 0, LINEF = 1 240 220 T = +85°C ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO (V = +3.6V +1.8V, V AVDD DVDD REFP are +25NC.) A INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE 3 3.0V 2.9 AVDD 2.8 2.7 2.6 LINEF = 0 ...
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Single-Channel, Ultra-Low-Power, AVDD DVDD GND AINP AINN 3RD-ORDER DELTA-SIGMA MODULATOR REFP REFN *PROGRAMMABLE GAIN ONLY AVAILABLE ON THE MAX11210. _______________________________________________________________________________________ Delta-Sigma ADCs with GPIO TIMING PROGRAMMABLE DIGITAL FILTER GAIN* 4 (SINC ) (1–16) MAX11200 MAX11210 Functional Diagram CLOCK GENERATOR ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO PIN NAME 1 GPIO1 General-Purpose I/O 1. Register controllable using SPI. 2 GPIO2 General-Purpose I/O 2. Register controllable using SPI. 3 GPIO3 General-Purpose I/O 3. Register controllable using SPI. 4 GND Ground. Ground ...
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Single-Channel, Ultra-Low-Power, Detailed Description The MAX11200/MAX11210 are ultra-low-power (< 300FA active), high-resolution, low-speed, serial-output ADCs. These ADCs provide the highest resolution per unit power in the industry, and are optimized for applications that require very high dynamic range with ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO provides maximum 50Hz rejection. See Figures 1 and 2. For optimal simultaneous 50Hz and 60Hz rejection, apply a 2.25275MHz external clock at CLK. The devices provide differential inputs REFP and REFN for an ...
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Single-Channel, Ultra-Low-Power, Table 3a. Example of Self-Calibration STEP DESCRIPTION 1 Initial power-up 2 Enable self-calibration registers 3 Self-calibration, DIN = 10010000 Table 3b. Example of System Calibration STEP DESCRIPTION 1 Initial power-up 2 Enable self-calibration registers 3 Self-calibration, DIN ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO NORMAL MODE REJECTION DATA RATE 10.0SPS 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 FREQUENCY (Hz) Figure 1. Normal-Mode Frequency ...
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Single-Channel, Ultra-Low-Power, MAX313 LOGIC SWITCH 0 OFF 1 ON IN1 IN2 AIN1 IN3 AIN2 IN4 AIN3 AIN4 MAX313 COM1 COM2 COM3 COM4 Figure 3. MAX11200 GPIOs Drive an External 4-Channel Switch (MAX313) Table 4c. Data Command to Select Channel ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO Serial-Digital Interface The MAX11200/MAX11210 interface is fully compatible with SPI-, QSPI-, and MICROWIRE-standard serial inter- faces. The SPI interface provides access to nine on-chip registers that are bits wide. Drive ...
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Single-Channel, Ultra-Low-Power, Communication between the user and the device is con- ducted through SPI using a command byte. The com- mand byte consists of two modes differentiated as com- mand modes and data modes. Command modes and data modes ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO Table 7. Operating Mode (MODE Bit) MODE BIT SETTING 0 The command byte initiates a conversion or an immediate power-down. See Tables 5 and 8. 1 The device interprets the command byte as ...
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Single-Channel, Ultra-Low-Power, Table 10. Register Address Map ADDRESS REGISTER SELECT B7 R/W NAME (RS[3:0]) STAT1 R 0x0 SYSOR CTRL1 0x1 LINEF R/W CTRL2 0x2 DIR4 R/W CTRL3 0x3 DGAIN2* R/W DATA R 0x4 SOC 0x5 R/W SGC 0x6 R/W ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO Table 11. STAT1 Register (Read Only) BIT B7 SYSOR BIT NAME DEFAULT 0 SYSOR: The system gain overrange bit when set to 1 indicates that a system gain calibration was over range. The ...
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Single-Channel, Ultra-Low-Power, The byte-wide CTRL1 register is a bidirectional read/write register. The byte written to the CTRL1 register indicates if the part converts continuously or single cycle external or internal clock is used, if the reference and ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO The byte-wide CTRL2 register is a bidirectional read/write register. The byte written to the CTRL2 register controls the direction and values of the digital I/O ports. Table 13. CTRL2 Register (Read/Write) BIT B7 ...
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Single-Channel, Ultra-Low-Power, The data register is a 24-bit read-only register. Any attempt to write data to the data register has no effect. The data read from this register is clocked out MSB first. The data register holds the conversion ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO Table 16b. Output Data Formats for the Bipolar Input Range INPUT VOLTAGE AINP AINN ≥ V REF × 1 − REF 23 2 ...
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Single-Channel, Ultra-Low-Power, The system gain calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB first. This register holds the system gain calibration value. The format is always in two’s complement binary ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO The self-calibration gain register is a 24-bit read/write register. The data written/read to/from this register is clocked in/ out MSB first. This register holds the self-calibration gain value. The format is always in ...
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Single-Channel, Ultra-Low-Power REF1 REF2 I REF2 REFP R REF MAX11200 I REF1 MAX11210 REFN AINP R RTD AINN GND Figure 8. RTD Temperature Measurement Circuit AVDD REFP REFN AINP AINN Figure 9. Resistive Bridge ...
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Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO LOAD ROBERVAL WEIGHING PAN FULCRUM FLEXURES FORCE COIL TENSION FLEXURE Figure 10. Typical Magnetic Force Restoration Scale For the latest package outline information and land patterns www.maxim-ic.com/packages. Note that a “+”, ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products © ...