PEX 8664-AA50BC F PLX Technology, PEX 8664-AA50BC F Datasheet

Peripheral Drivers & Components (PCIs) 64Ln/16Pt PCI Exprss Gen 2 (5 GT/s) Swtch

PEX 8664-AA50BC F

Manufacturer Part Number

PEX 8664-AA50BC F

Description

Peripheral Drivers & Components (PCIs) 64Ln/16Pt PCI Exprss Gen 2 (5 GT/s) Swtch

Manufacturer

PLX Technology

Datasheet

1.PEX_8664-AA50BC_F.pdf (5 pages)

Specifications of PEX 8664-AA50BC F

Mounting Style

SMD/SMT

Propagation Delay Time

176 ns

Package / Case

HFCBGA-1156

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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Features

o 64-lane, 16-port PCIe Gen2 switch

o 35 x 35mm

o Typical Power: 7.9 Watts

o Standards Compliant

o High Performance

o Flexible Configuration

o Multi-Host & Fail-Over Support

o Quality of Service (QoS)

o Reliability, Availability, Serviceability

PEX 8664 General Features

PEX 8664 Key Features

- Integrated 5.0 GT/s SerDes

- PCI Express Base Specification, r2.0

- PCI Power Management Spec, r1.2

- Microsoft Vista Compliant

- Supports Access Control Services

- Dynamic link-width control

- Dynamic SerDes speed control

♦ performancePAK

- Non-blocking switch fabric

- Full line rate on all ports

- Packet Cut-Thru with 176ns max packet

- 2KB Max Payload Size

- Ports configurable as x1, x2, x4, x8, x16

- Registers configurable with strapping

- Lane and polarity reversal

- Compatible with PCIe 1.0a PM

- Configurable Non-Transparent (NT) port

- Failover with NT port

- Up to Five upstream/Host ports with 1+1

- Eight traffic classes per port

- Weighted round-robin source

♦ visionPAK

- 4 Hot Plug Ports with native HP Signals

- All ports hot plug capable thru I

- ECRC and Poison bit support

- Data Path parity

- Memory (RAM) Error Correction

- INTA# and FATAL_ERR# signals

- Advanced Error Reporting

- Port Status bits and GPIO available

- Per port error diagnostics

(backwards compatible w/ PCIe r1.0a/1.1)

latency (x16 to x16)

pins, EEPROM, I

or N+1 failover to other upstream ports

port arbitration

(Hot Plug Controller on every port)

JTAG AC/DC boundary scan

Read Pacing (bandwidth throttling)

Multicast

Dynamic Buffer/FC Credit Pool

Per Port Performance Monitoring

SerDes Eye Capture

Error Injection and Loopback

Per port payload & header counters

, 1156-ball FCBGA package

C, or host software

PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports

The ExpressLane

switching capability enabling users to connect multiple hosts to their

respective endpoints via scalable, high bandwidth, non-blocking

interconnection to a wide variety of applications including servers,

storage systems, and communications platforms. The PEX 8664 is

well suited for fan-out, aggregation, and peer-to-peer applications.

Multi-Host Architecture

The PEX 8664 employs an enhanced version of PLX’s field tested PEX 8648

PCIe switch architecture, which allows users to configure the device in

legacy single-host mode or multi-host mode with up to five host ports

capable of 1+1 (one active & one backup) or N+1 (N active & one backup)

host failover. This powerful architectural enhancement enables users to build

PCIe based systems to support high-availability, failover, redundant and

clustered systems.

High Performance & Low Packet Latency

The PEX 8664 architecture supports packet cut-thru with a maximum

latency of 176ns (x16 to x16). This, combined with large packet memory,

flexible common buffer/FC credit pool and non-blocking internal switch

architecture, provides full line rate on all ports for performance-hungry

applications such as servers and switch fabrics. The low latency enables

applications to achieve high throughput and performance. In addition to low

latency, the device supports a packet payload size of up to 2048 bytes,

enabling the user to achieve even higher throughput.

Data Integrity

The PEX 8664 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction circuitry

throughout the internal data paths as packets pass through the switch.

Flexible Configuration

The PEX 8664’s 16 ports can be

configured to lane widths of x1, x2, x4,

x8, or x16. Flexible buffer allocation,

along with the device's flexible packet

flow control, maximizes throughput

for applications where more traffic

flows in the downstream, rather than

upstream, direction. Any port can be

designated as the upstream port, which

can be changed dynamically. Figure 1

shows some of the PEX 8664’s

common port configurations in legacy

Single-Host mode.

Page 1 of 1

PEX 8664 device offers Multi-Host PCI Express

Figure 1. Common Port Configurations

2 x8

PEX 8664

15 x4

10 x4

5/14/2009, Version 1.1

5 x8

PEX 8664

6 x8

x16

4 x4

Related parts for PEX 8664-AA50BC F

PEX 8664-AA50BC F Summary of contents

Page 1

... Multi-Host Architecture The PEX 8664 employs an enhanced version of PLX’s field tested PEX 8648 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with up to five host ports capable of 1+1 (one active & ...

Page 2

... Interoperability The PEX 8664 is designed to be fully compliant with the PCI Express Base Specification r2.0, and is backwards compatible to PCI Express Base Specification r1.1 and r1.0a. Additionally, it supports auto-negotiation, lane reversal, and polarity reversal ...

Page 3

... Performance Monitoring, SerDes Eye Capture, Error Injection, SerDes Loopback, and more. © PLX Technology, www.plxtech.com PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports Performance Monitoring The PEX 8664’s real time performance monitoring allows users to literally “see” ingress and egress performance on each port as traffic passes through the switch using PLX’ ...

Page 4

... Figure 8, two hosts may be active simultaneously and controlling their own domains while exchange status © PLX Technology, www.plxtech.com PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports information through doorbell registers or I The devices can be programmed to trigger fail-over if the heartbeat information is not provided. In the event of ...

Page 5

... The PEX 8664 RDK (see Figure 10 hardware module containing the PEX 8664 which plugs right into your system. The PEX 8664 RDK can be used to test and validate customer software, or used as an evaluation vehicle for PEX 8664 features and benefits. The PEX 8664 RDK provides everything that a user needs to get their hardware and software development started ...

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