PEX 8680-AA50BC F PLX Technology, PEX 8680-AA50BC F Datasheet - Page 3

• Manufacturer Part Number: PEX 8680-AA50BC F
• Description: Peripheral Drivers & Components (PCIs) 80Ln/20Pt PCI Exprss Gen 2 (5 GT/s) Swtch
• Manufacturer: PLX Technology

Specifications of PEX 8680-AA50BC F

• Mounting Style: SMD/SMT
• Propagation Delay Time: 176 ns
• Package / Case: HFCBGA-1156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

r1.0a. Additionally, it supports auto-negotiation, lane
reversal, and polarity reversal. Furthermore, the PEX
8680 is tested for Microsoft Vista compliance. All PLX
switches undergo thorough interoperability testing in
PLX’s Interoperability Lab and compliance testing at
the PCI-SIG plug-fest.
performancePAK
Exclusive to PLX, performancePAK is a suite of unique
and innovative performance features which allows
PLX’s Gen 2 switches to be the highest performing Gen
2 switches in the market today. The performancePAK
features consists of the Read Pacing, Multicast, and
Dynamic Buffer Pool.
Read Pacing
The Read Pacing feature allows users to throttle the
amount of read requests being made by downstream
devices. When a downstream device requests several
long reads back-to-back, the Root Complex gets tied up
in serving that downstream port. If that port has a narrow
link and is therefore slow in receiving these read packets
from the Root Complex, then other downstream ports
may become starved – thus, impacting performance. The
Read Pacing feature enhances performances by allowing
for the adequate servicing of all downstream devices.
Multicast
The Multicast feature enables the copying of data
(packets) from one ingress port to multiple (up to 19)
egress ports in one transaction allowing for higher
performance in dual-graphics, storage, security, and
redundant applications, among others. Multicast relieves
the CPU from having to conduct multiple redundant
transactions, resulting in higher system performance.
Dynamic Buffer Pool
The PEX 8680 employs a dynamic buffer pool for Flow
Control (FC) management. As opposed to a static buffer
scheme which assigns fixed, static buffers to each port,
PLX’s dynamic buffer allocation scheme utilizes a
common pool of FC Credits which are shared by other
ports. This shared buffer pool is fully programmable by
the user, so FC credits can be allocated among the ports
as needed. Not only does this prevent wasted buffers and
inappropriate buffer assignments, any unallocated
buffers remain in the common buffer pool and can then
be used for faster FC credit updates.
© PLX Technology, www.plxtech.com
TM
PEX 8680, PCI Express Gen 2 Switch, 80 Lanes, 20 Ports
Page 3 of 3
visionPAK
Another PLX exclusive, visionPAK is a debug
diagnostics suite of integrated hardware and software
instruments that users can use to help bring their systems
to market faster. visionPAK features consist of
Performance Monitoring, SerDes Eye Capture, Error
Injection, SerDes Loopback, and more.
Performance Monitoring
The PEX 8680’s real time performance monitoring
allows users to literally “see” ingress and egress
performance on each port as traffic passes through the
switch using PLX’s Software Development Kit (SDK).
The monitoring is completely passive and therefore has
no affect on overall system performance. Internal
counters provide extensive granularity down to traffic &
packet type and even allows for the filtering of traffic
(i.e. count only Memory Writes).
SerDes Eye Capture
Users can evaluate their system’s signal integrity at the
physical layer using the PEX 8680’s SerDes Eye
Capture feature. Using PLX’s SDK, users can view the
receiver eye of any lane on the switch. Users can then
modify SerDes settings and see the impact on the
receiver eye. Figure 5 shows a screenshot of the SerDes
Eye Capture feature in the SDK.
Error Injection & SerDes Loopback
Using the PEX 8680’s Error Injection feature, users can
inject malformed packets and/or fatal errors into their
system and evaluate a system’s ability to detect and
recover from such errors. The PEX 8680 also supports
Internal Tx, External Tx, Recovered Clock, and
Recovered Data Loopback modes.
Figure 5. SerDes Eye Capture
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5/14/2009, Version 1.1