LCMXO256C-3TN100I Lattice, LCMXO256C-3TN100I Datasheet
LCMXO256C-3TN100I
Specifications of LCMXO256C-3TN100I
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LCMXO256C-3TN100I Summary of contents
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... The ispLEVER design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verifi ...
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... Lattice Semiconductor Table 2-8. I/O Support Device by Device MachXO256 Number of I/O Banks 2 Single-ended (all I/O Banks) Type of Input Buffers Single-ended buffers with complementary outputs (all I/O Banks) Types of Output Buffers Differential Output All I/O Banks Emulation Capability PCI Support No Table 2-9. Supported Input Standards ...
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... Lattice Semiconductor Table 2-10. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain 3 PCI33 Differential Interfaces 1, 2 LVDS 2 BLVDS, RSDS 2 LVPECL 1. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers. ...
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... Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. ...
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... Lattice Semiconductor MachXO1200 and MachXO2280 Hot Socketing Specifications Symbol Parameter Non-LVDS General Purpose sysIOs I Input or I/O Leakage Current DK LVDS General Purpose sysIOs I Input or I/O Leakage Current DK_LVDS 1. Insensitive to sequence CC, CCAUX ≤ V ≤ V (MAX), 0 ≤ V ≤ CCIO CCIO additive PU LVCMOS and LVTTL only. ...
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... CCIO 1, 2 Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C 4 All LCMXO ‘C’ Devices Over Recommended Operating Conditions Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256E/C LCMXO640E/C LCMXO1200E/C LCMXO2280E/C 6 All devices 3-3 DC and Switching Characteristics MachXO Family Data Sheet 3 Typ ...
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... Assumes all I/O pins are held at V CCIO 3. Frequency = 0MHz. 4. Typical user pattern power supplies at nominal voltage Per Bank 2.5V. Does not include pull-up/pull-down. CCIO Over Recommended Operating Conditions Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256E/C LCMXO640E/C LCMXO1200E/C LCMXO2280E/C 6 All devices or GND. ...
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... JTAG programming is at 25MHz 25°C, power supplies at nominal voltage Per Bank 2.5V. Does not include pull-up/pull-down. CCIO Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256C/E LCMXO640C/E LCMXO1200/E LCMXO2280C/E 6 All devices or GND. 3-5 DC and Switching Characteristics MachXO Family Data Sheet Typ. Units 9 mA ...
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... Lattice Semiconductor sysIO Recommended Operating Conditions Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 LVTTL 3 PCI 1, 2 LVDS 1 LVPECL 1 BLVDS 1 RSDS 1. Inputs on chip. Outputs are implemented with the addition of external resistors. 2. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers 3 ...
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... Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 0.8 LVTTL -0.3 0.8 LVCMOS 2.5 -0.3 0.7 LVCMOS 1.8 -0.3 0.35V CCIO LVCMOS 1.5 -0.3 0.35V CCIO LVCMOS 1.2 -0.3 0.42 (“C” Version) LVCMOS 1.2 -0 ...
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... Lattice Semiconductor MachXO External Switching Characteristics Parameter Description General I/O Pin Parameters (Using Global Clock without PLL) t Best Case t Through 1 LUT Best Case Clock to Output - From PFU CO t Clock to Data Setup - To PFU SU t Clock to Data Hold - To PFU H f Clock Frequency of I/O and PFU Register ...
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... Lattice Semiconductor MachXO Internal Timing Parameters Parameter Description PFU/PFF Logic Mode Timing t LUT4 delay ( inputs to F output) LUT4_PFU t LUT6 delay ( inputs to OFX output) LUT6_PFU t Set/Reset to output of PFU LSR_PFU t Clock to Mux (M0,M1) input setup time SUM_PFU t Clock to Mux (M0,M1) input hold time ...
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... Lattice Semiconductor MachXO Family Timing Adders Buffer Type Input Adjusters 4 LVDS25 LVDS 4 BLVDS25 BLVDS 4 LVPECL33 LVPECL LVTTL33 LVTTL LVCMOS33 LVCMOS 3.3 LVCMOS25 LVCMOS 2.5 LVCMOS18 LVCMOS 1.8 LVCMOS15 LVCMOS 1.5 LVCMOS12 LVCMOS 1.2 4 PCI33 PCI Output Adjusters LVDS25E LVDS 2 LVDS25 LVDS 2.5 BLVDS25 BLVDS 2 ...
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... Lattice Semiconductor sysCLOCK PLL Timing Parameter Descriptions f Input Clock Frequency (CLKI, CLKFB Output Clock Frequency (CLKOP, CLKOS) OUT f K-Divider Output Frequency (CLKOK) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t Output Clock Duty Cycle Output Phase Accuracy Output Clock Period Jitter ...
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... Lattice Semiconductor Flash Download Time Symbol Minimum CCAUX t (later of the two supplies) REFRESH to Device I/O Active JTAG Port Timing Specifications Symbol f TCK [BSCAN] clock frequency MAX t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH t TCK [BSCAN] clock pulse width low ...
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Part Number Description LCMXO XXXX X – X XXXXXX X XX Device Family MachXO PLD Logic Capacity 256 LUTs = 256 640 LUTs = 640 1200 LUTs = 1200 2280 LUTs = 2280 Supply Voltage C = 1.8V/2.5V/3. ...
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... Lattice Semiconductor Lead-Free Packaging Part Number LUTs LCMXO256C-3TN100I 256 LCMXO256C-4TN100I 256 LCMXO256C-3MN100I 256 LCMXO256C-4MN100I 256 Part Number LUTs LCMXO640C-3TN100I 640 LCMXO640C-4TN100I 640 LCMXO640C-3MN100I 640 LCMXO640C-4MN100I 640 LCMXO640C-3TN144I 640 LCMXO640C-4TN144I 640 LCMXO640C-3MN132I 640 LCMXO640C-4MN132I 640 LCMXO640C-3FTN256I 640 LCMXO640C-4FTN256I 640 Part Number LUTs ...