LCMXO256C-4TN100C Lattice, LCMXO256C-4TN100C Datasheet - Page 5
![CPLD - Complex Programmable Logic Devices 256 LUTs 78 IO 1.8/2 .5/3.3V -4 Spd](/photos/16/2/160258/tqfp-100_sml.jpg)
LCMXO256C-4TN100C
Manufacturer Part Number
LCMXO256C-4TN100C
Description
CPLD - Complex Programmable Logic Devices 256 LUTs 78 IO 1.8/2 .5/3.3V -4 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO640C-3TN100C.pdf
(95 pages)
Specifications of LCMXO256C-4TN100C
Memory Type
SRAM
Number Of Macrocells
128
Maximum Operating Frequency
550 MHz
Delay Time
4.2 ns
Number Of Programmable I/os
78
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
13 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Programmable Type
*
Voltage - Input
*
Speed
*
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO256C-4TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO256C-4TN100C
Manufacturer:
LATTICE
Quantity:
20 000
Company:
Part Number:
LCMXO256C-4TN100C-3I
Manufacturer:
SHARP
Quantity:
15 600
Part Number:
LCMXO256C-4TN100C-3I
Manufacturer:
LATTICE
Quantity:
20 000
Lattice Semiconductor
Figure 2-1. Top View of the MachXO1200 Device
1. Top view of the MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks.
Figure 2-2. Top View of the MachXO640 Device
sysMEM Embedded
Block RAM (EBR)
sysCLOCK
PLL
JTAG Port
Programmable
Function Units
with RAM (PFUs)
JTAG Port
PIOs Arranged into
sysIO Banks
1
2-2
Programmable
Function Units
without RAM (PFFs)
MachXO Family Data Sheet
PIOs Arranged into
sysIO Banks
Programmable
Functional Units
without RAM (PFFs)
Programmable
Functional Units
with RAM (PFUs)
Architecture