LCMXO2280C-4FTN324C Lattice, LCMXO2280C-4FTN324C Datasheet - Page 3
LCMXO2280C-4FTN324C
Manufacturer Part Number
LCMXO2280C-4FTN324C
Description
CPLD - Complex Programmable Logic Devices 2280 LUTs 271 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO640C-3TN100C.pdf
(95 pages)
Specifications of LCMXO2280C-4FTN324C
Memory Type
SRAM
Number Of Macrocells
1140
Maximum Operating Frequency
550 MHz
Delay Time
4.4 ns
Number Of Programmable I/os
271
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
23 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
FTBGA-324
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Programmable Type
*
Voltage - Input
*
Speed
*
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2280C-4FTN324C
Manufacturer:
SKYWORKS
Quantity:
300
Company:
Part Number:
LCMXO2280C-4FTN324C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LCMXO2280C-4FTN324C-3I
Manufacturer:
NS
Quantity:
70
Part Number:
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Manufacturer:
LATTICE
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Introduction
Lattice Semiconductor
MachXO Family Data Sheet
The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex-
ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-
security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and
careful design will provide the high pin-to-pin performance also associated with CPLDs.
®
The ispLEVER
design tools from Lattice allow complex designs to be efficiently implemented using the MachXO
family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools
use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in
the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design
for timing verification.
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