LC4064V-75TN44C Lattice, LC4064V-75TN44C Datasheet - Page 33

• Manufacturer Part Number: LC4064V-75TN44C
• Description: CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
• Manufacturer: Lattice
• Series: ispMACH®r

Specifications of LC4064V-75TN44C

• Memory Type: EEPROM
• Number Of Macrocells: 64
• Number Of Product Terms Per Macro: 80
• Maximum Operating Frequency: 400 MHz
• Delay Time: 2.5 ns
• Number Of Programmable I/os: 388
• Operating Supply Voltage: 3.3 V
• Supply Current: 12 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Programmable Type: CPLD
• Voltage - Input: 3 V ~ 3.6 V
• Speed: 7.5ns
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ispMACH 4000Z Internal Timing Parameters (Cont.)
Lattice Semiconductor
In/Out Delays
t
t
t
t
t
t
Routing/GLB Delays
t
t
t
t
t
t
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Control Delays
t
t
t
t
t
Parameter
IN
GOE
GCLK_IN
BUF
EN
DIS
ROUTE
MCELL
INREG
FBK
PDb
PDi
S
S_PT
ST
ST_PT
H
HT
SIR
SIR_PT
HIR
HIR_PT
COi
CES
CEH
SL
SL_PT
HL
GOi
PDLi
SRi
SRR
BCLK
PTCLK
BSR
PTSR
GPTOE
Input Buffer Delay
Global OE Pin Delay
Global Clock Input Buffer Delay
Delay through Output Buffer
Output Enable Time
Output Disable Time
Delay through GRP
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
5-PT Bypass Propagation Delay
Macrocell Propagation Delay
D-Register Setup Time (Global Clock)
D-Register Setup Time (Product Term Clock)
T-Register Setup Time (Global Clock)
T-register Setup Time (Product Term Clock)
D-Register Hold Time
T-Resister Hold Time
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
Clock Enable Hold Time
Latch Setup Time (Global Clock)
Latch Setup Time (Product Term Clock)
Latch Hold Time
Latch Gate to Output/Feedback MUX Time
Propagation Delay through Transparent Latch to Output/
Feedback MUX
Asynchronous Reset or Set to Output/Feedback MUX Delay
Asynchronous Reset or Set Recovery Delay
GLB PT Clock Delay
Macrocell PT Clock Delay
GLB PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Global PT OE Delay
Description
Over Recommended Operating Conditions
33
ispMACH 4000V/B/C/Z Family Data Sheet
Min.
1.00
2.10
1.20
2.30
1.90
1.90
1.30
1.45
1.30
1.00
2.00
0.00
1.00
2.10
2.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-45
Max.
0.95
3.00
1.95
1.10
2.50
2.50
2.25
0.65
1.00
0.35
0.20
0.45
0.75
0.33
0.25
0.97
1.80
1.55
1.55
1.83
1.83
4.30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
1.10
1.90
1.30
2.10
1.90
1.90
1.10
1.45
1.50
1.00
2.00
0.00
1.00
1.90
2.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
Max.
1.25
3.50
2.05
1.00
2.50
2.50
2.05
0.65
1.00
0.05
0.70
0.65
1.15
0.33
0.25
0.97
1.80
1.55
1.55
1.83
1.83
4.20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
1.35
2.45
1.55
2.75
3.15
3.15
0.75
1.45
1.95
1.18
2.00
0.00
1.65
2.15
1.17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-75
Max.
1.80
4.30
2.15
1.30
2.70
2.70
2.50
1.00
1.00
0.05
1.90
1.00
1.05
0.33
0.25
0.28
1.67
1.25
1.25
1.83
2.72
3.50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns