A2F200M3F-1FGG484 Actel, A2F200M3F-1FGG484 Datasheet - Page 21

• Manufacturer Part Number: A2F200M3F-1FGG484
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG484

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 161
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the
airflow where the device is mounted should be increased. The design's total junction-to-air thermal
resistance requirement can be estimated by
Determining the heat sink's thermal performance proceeds as follows:
where
A heat sink with a thermal resistance of 5.01°C/W or better should be used. Thermal resistance of heat
sinks is a function of airflow. The heat sink performance can be significantly improved with increased
airflow.
Carefully estimating thermal resistance is important in the long-term reliability of an FPGA. Design
engineers should always correlate the power consumption of the device with the maximum allowable
power dissipation of the package selected for that device.
Note:
Temperature and Voltage Derating Factors
Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays
θ
θ
Array
Voltage
VCC (V)
1.425
1.500
1.575
JA
SA
=
=
=
The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard
(JESD-51) and assumptions made in building the model. It may not be realized in actual
application and therefore should be used with a degree of caution. Junction-to-case thermal
resistance assumes that all power is dissipated through the case.
0.37°C/W
Thermal resistance of the interface material between
the case and the heat sink, usually provided by the
thermal interface manufacturer
Thermal resistance of the heat sink in °C/W
(normalized to T
–40°C
0.81
0.78
0.86
θ
SA
θ
JA(total)
=
J
13.33°C/W 8.28°C/W
P
= 85°C, worst-case VCC = 1.425 V)
=
0.91
0.86
0.83
0°C
=
T
------------------ -
θ
θ
T
------------------ -
J
JA(TOTAL)
SA
θ
J
–
JA
–
P
T
=
A
T
–
A
EQ
θ
R e v i s i o n 6
=
Junction Temperature (°C)
JA(TOTAL)
=
100°C 70°C
----------------------------------- -
7:
=
100°C 70°C
----------------------------------- -
25°C
0.93
0.88
0.85
17.00 W
θ
3.00 W
JC
–
–
+
–
–
0.37°C/W
θ
θ
CS
JC
SmartFusion Intelligent Mixed Signal FPGAs
–
+
=
θ
θ
=
CS
SA
70°C
0.98
0.93
0.90
1.76 W
10.00°C/W
=
5.01°C/W
85°C
1.00
0.95
0.91
100°C
1.02
0.96
0.93
EQ 6
EQ 7
EQ 8
EQ 9
2 -9