AGL125V2-QNG132 Actel, AGL125V2-QNG132 Datasheet - Page 102
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AGL125V2-QNG132
Manufacturer Part Number
AGL125V2-QNG132
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL125V2-QNG132
Processor Series
AGL125
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
84
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
125 K
Package / Case
QFN-132
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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IGLOO DC and Switching Characteristics
Table 2-155 • Parameter Definition and Measuring Nodes
2- 88
Parameter Name
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OREMCLR
ORECCLR
OECLKQ
OESUD
OEHD
OESUE
OEHE
OECLR2Q
OEREMCLR
OERECCLR
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IREMCLR
IRECCLR
*See
Figure 2-17 on page 2-87
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
for more information.
Parameter Definition
R ev i sio n 1 8
Measuring Nodes
(from, to)*
HH, DOUT
HH, EOUT
LL, DOUT
II, EOUT
GG, HH
GG, HH
CC, AA
DD, AA
KK, HH
KK, HH
AA, EE
CC, AA
BB, AA
DD, EE
DD, AA
FF, HH
FF, HH
LL, HH
LL, HH
BB, AA
JJ, HH
JJ, HH
II, HH
II, HH
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