A3P060-FGG144 Actel, A3P060-FGG144 Datasheet - Page 36
A3P060-FGG144
Manufacturer Part Number
A3P060-FGG144
Description
FPGA - Field Programmable Gate Array 60K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P060-FGG144
Processor Series
A3P060
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
96
Data Ram Size
18432
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
60 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P060-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3P060-FGG144T
Manufacturer:
Microsemi SoC
Quantity:
10 000
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ProASIC3 DC and Switching Characteristics
2- 22
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-22 • Summary of AC Measuring Points
Table 2-23 • I/O AC Parameter Definitions
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
Parameter
t
t
t
t
t
t
t
t
t
t
t
DP
PY
DOUT
EOUT
DIN
HZ
ZH
LZ
ZL
ZHS
ZLS
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
Enable to Pad delay through the Output Buffer—Z to Low
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
R e visio n 9
Parameter Definition
Measuring Trip Point (V
0.285 * VCCI (RR)
0.285 * VCCI (RR)
0.615 * VCCI (FF)
0.615 * VCCI (FF)
0.90 V
0.75 V
1.4 V
1.4 V
1.2 V
trip
)
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