AGL250V2-VQG100 Actel, AGL250V2-VQG100 Datasheet - Page 2
![FPGA - Field Programmable Gate Array 250K System Gates](/photos/16/15/161502/landingpageacteligloofpga_sml.jpg)
AGL250V2-VQG100
Manufacturer Part Number
AGL250V2-VQG100
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL250V2-VQG100
Processor Series
AGL250
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
68
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL250V2-VQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL250V2-VQG100
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
AGL250V2-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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I/Os Per Package
Table 1 • IGLOO FPGAs Package Sizes Dimensions
IGLOO Devices
ARM-Enabled
IGLOO Devices
Package
QN48
QN68
UC81
CS81
CS121
VQ100
QN132
CS196
FG144
FG256
CS281
FG484
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the
2. The M1AGL250 device does not support QN132 or CS196 packages. Refer to the
3. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
4. Device/package support TBD.
5. FG256 and FG484 are footprint-compatible packages.
6. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
7. "G" indicates RoHS-compliant packages. Refer to
Package
Length × Width
(mm\mm)
Nominal Area
(mm
Pitch (mm)
Height (mm)
IGLOO Low Power Flash FPGAs
I I
ensure compliance with design and board migration requirements.
position assignments of the 15 LVPECL pairs.
ended user I/Os available is reduced by one.
part number.
2
)
5
5
AGL015
UC81
4 × 4
0.80
0.4
16
49
–
–
–
–
–
–
–
–
–
–
–
CS81
5 × 5
0.80
0.5
25
AGL030
1
34
49
66
66
77
81
–
–
–
–
–
–
CS121
6 × 6
0.99
0.5
36
AGL060
96
96
71
80
–
–
–
–
–
–
–
–
4
QN68
8 × 8
0.90
0.4
64
AGL125
"IGLOO Ordering Information" on page III
133
71
84
97
–
–
–
–
–
–
–
–
QN132
8 × 8
0.75
0.5
64
R evis i o n 18
87
143
M1AGL250
68
97
–
–
–
–
–
–
–
–
CS196
8 × 8
AGL250
1.20
4
I/O Type
0.5
64
19
13
35
24
–
–
–
–
–
–
–
–
10 × 10
CS281
2
4
1.05
100
0.5
M1AGL400
143
178
194
97
–
–
–
–
–
–
–
–
AGL400
13 × 13
FG144
IGLOO FPGA Fabric User’s Guide
1.45
169
1.0
IGLOO FPGA Fabric User’s Guide
35
25
38
38
–
–
–
–
–
–
–
–
for the location of the "G" in the
14 × 14
VQ100
M1AGL600
177
215
235
97
1.00
–
–
–
–
–
–
–
–
196
AGL600
0.5
25
43
53
60
–
–
–
–
–
–
–
–
17 × 17
FG256
1.60
289
1.0
M1AGL1000
177
215
300
97
AGL1000
–
–
–
–
–
–
–
–
23 × 23
FG484
2.23
529
1.0
25
44
53
74
–
–
–
–
–
–
–
–
for
to
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