LFEC3E-3QN208C Lattice, LFEC3E-3QN208C Datasheet - Page 30

• Manufacturer Part Number: LFEC3E-3QN208C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs
• Manufacturer: Lattice

Specifications of LFEC3E-3QN208C

• Number Of Macrocells: 3100
• Number Of Programmable I/os: 145
• Data Ram Size: 56320
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-32. DQS Local Bus.
Figure 2-33. DLL Calibration Bus and DQS/DQS Transition Distribution
Control
Polarity
Control
Delay
DQS
Bus
Bus
Bus
Delay Control Bus
DQS
DQS
CLKI
GSR
DQS
CEI
DLL
DLL
To DDR
Reg.
Polarity Control
Register Block
( 5 Flip Flops)
2-27
PIO
PIO
DQSDEL
Logic
Input
To Sync.
Calibration Bus
from DLL
Reg.
LatticeECP/EC Family Data Sheet
Polarity Control Bus
Buffer
Buffer
sysIO
sysIO
DI
DI
DQS Bus
Datain
Strobe
DDR
DQS
PAD
PAD
Architecture