APA075-TQG100 Actel, APA075-TQG100 Datasheet - Page 67

FPGA - Field Programmable Gate Array 75K System Gates

APA075-TQG100

Manufacturer Part Number
APA075-TQG100
Description
FPGA - Field Programmable Gate Array 75K System Gates
Manufacturer
Actel
Datasheet

Specifications of APA075-TQG100

Processor Series
APA075
Core
IP Core
Maximum Operating Frequency
150 MHz
Number Of Programmable I/os
158
Data Ram Size
27648
Supply Voltage (max)
2.7 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
2.3 V
Number Of Gates
75 K
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
APA075-TQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
APA075-TQG100
Manufacturer:
ACTEL
Quantity:
20 000
Part Number:
APA075-TQG100A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
APA075-TQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
APA075-TQG100I
Manufacturer:
XILINX
0
Part Number:
APA075-TQG100I
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Asynchronous SRAM Write
Note: The plot shows the normal operation status.
Figure 2-30 • Asynchronous SRAM Write
Table 2-54 • T
Symbol t
AWRH
AWRS
DWRH
DWRS
DWRS
WPDA
WPDH
WRCYC
WRMH
WRML
xxx
T
J
J
= 0°C to 110°C; V
= –55°C to 150°C, V
DI setup to WB ↑
DI setup to WB ↑
WADDR hold from WB ↑
WADDR setup to WB ↓
DI hold from WB ↑
WPE access from DI
WPE hold from DI
Cycle time
WB high phase
WB low phase
WRB, WBLKB
Description
WADDR
DD
WPE
DD
= 2.3 V to 2.7 V for Commercial/Industrial
t AWRS
DI
t WPDA
= 2.3 V to 2.7 V for Military/MIL-STD-883B
t WRML
Min.
v5.9
1.0
0.5
1.5
0.5
2.5
3.0
7.5
3.0
3.0
t DWRS
t WRCYC
Max.
1.0
t WRMH
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ProASIC
t AWRH
t DWRH
t WPDH
PARGEN is inactive.
PARGEN is active.
WPE is invalid, while PARGEN is
active.
Inactive
Active
PLUS
Flash Family FPGAs
Notes
2-57

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