LFXP3C-5TN100C Lattice, LFXP3C-5TN100C Datasheet - Page 226
LFXP3C-5TN100C
Manufacturer Part Number
LFXP3C-5TN100C
Description
FPGA - Field Programmable Gate Array 3.1K LUTS 62 I/O
Manufacturer
Lattice
Specifications of LFXP3C-5TN100C
Number Of Programmable I/os
62
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-5TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Table 10-5. DQSBUFB Ports
Notes:
READ Pulse Generation
The READ signal to the DQSBUFB block is internally generated in the FPGA core. The Read signal will go high
when the READ command to control the DDR SDRAM is initially asserted. This should normally precede the DQS
preamble by one cycle yet may overlap the trailing bits of a prior read cycle. The DQS Detect circuitry of the Lat-
ticeECP/EC and LatticeXP devices require the falling edge of the READ signal to be placed within the preamble
stage.
The preamble state of the DQS can be detected using the CAS latency and the round trip delay for the signals
between the FPGA and the memory device. Note that the internal FPGA core generates the READ pulse. The rise
of the READ pulse needs to coincide with the initial READ Command of the Read Burst and needs to go low before
the Preamble goes high.
Figure 10-8 shows the READ Pulse Timing Example with respect to the PRMBDET signal.
Figure 10-8. READ Pulse Generation
1. The DDR Clock Polarity output from this block should be connected to the DDCLKPOL inputs of the input
OK
FAIL
FAIL
OK
register blocks (IDDRXB).
PRMBDET
DQSI
CLK
READ
DQSDEL
DQSO
DQSC
DDRCLKPOL
PRMBDET
Port Name
READ
READ
READ
READ
DQS
PRIOR READ CYCLE
I/O
O
O
O
O
I
I
I
I
POSTAMBLE
DQS strobe signal from memory
System CLK
Read generated from the FPGA core
DQS delay from the DQSDLL primitive
Delayed DQS Strobe signal, to the input capture register block
DQS Strobe signal before delay, going to the FPGA core logic
DDR Clock Polarity signal
Preamble detect signal, going to the FPGA core logic
PREAMBLE
VTH
10-7
TRANSITION
FIRST DQS
Definition
LatticeECP/EC and LatticeXP
DDR Usage Guide
POSTAMBLE
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