APA300-PQG208 Actel, APA300-PQG208 Datasheet
APA300-PQG208
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APA300-PQG208 Summary of contents
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... In-System Programming (ISP) via JTAG Port SRAMs and FIFOs • SmartGen Netlist Generation Ensures Optimal Usage of ® ) Embedded Memory Blocks • 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical) 1 APA075 APA150 APA300 75,000 150,000 300,000 3,072 6,144 8,192 27 k 36k ...
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... Flash Family FPGAs Ordering Information _ APA1000 FG Speed Grade Blank = Standard Speed Part Number APA075 = 75,000 Equivalent System Gates APA150 = 150,000 Equivalent System Gates APA300 = 300,000 Equivalent System Gates APA450 = 450,000 Equivalent System Gates APA600 = 600,000 Equivalent System Gates APA750 = 750,000 Equivalent System Gates ...
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... Device 100-Pin 144-Pin 208-Pin 456-Pin APA075 66 107 158 APA150 66 158 5 APA300 158 APA450 158 5 APA600 158 APA750 158 5 APA1000 158 Notes: 1. Package Definitions: TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array, CQFP = Ceramic Quad Flat Pack, CCGA = Ceramic Column Grid Array, LGA = Land Grid Array 2 ...
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... Flash Family FPGAs Temperature Grade Offerings Package TQ100 TQ144 PQ208 BG456 FG144 FG256 FG484 FG676 FG896 FG1152 CQ208 CQ352 CG624 Note Commercial I = Industrial M = Military B = MIL-STD-883 Speed Grade and Temperature Matrix Note Commercial I = Industrial M = Military B = MIL-STD-883 iv APA075 APA150 APA300 v5.9 APA450 APA600 APA750 ...
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... PLUS The ProASIC family of devices, Actel’s second- generation family of flash FPGAs, offers enhanced performance over Actel’s ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, ...
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PLUS ProASIC Flash Family FPGAs PLUS ProASIC Architecture PLUS The proprietary ProASIC architecture granularity comparable to gate arrays. PLUS The ProASIC device core consists of a Sea-of-Tiles (Figure 1-1). Each tile can be configured as a three-input logic function (e.g., ...
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... (CLK (Reset) Figure 1-3 • Core Logic Tile Live at Power-Up PLUS The Actel flash-based ProASIC Level 0 of the live at power-up (LAPU) classification standard. This feature helps in system component initialization, executing critical processor wakes up, setting up and configuring memory blocks, clock generation, and bus activity management. ...
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... The Actel products described in this advance status datasheet may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life- support, and other high-reliability applications. Consult Actel’ ...
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... FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59 1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Export Administration Regulations (EAR 4-8 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . 2-51 v5.9 PLUS ...
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General Description Routing Resources PLUS The routing structure of ProASIC to provide high performance through a flexible four- level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very long-line resources, and high performance global networks. The ultra-fast ...
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PLUS ProASIC Flash Family FPGAs Spans 4 Tiles Figure 2-2 • Efficient Long-Line Resources 2 -2 Spans 2 Tiles Spans 1 Tile ...
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... Users can also drastically reduce delay penalties and save buffering resources by mapping critical high fanout nets to spines. For design hints on using these features, refer to Actel’s ProASIC Clock Trees v5.9 PLUS ...
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... Note: This figure shows routing for only one global path. Figure 2-4 • High-Performance Global Network Table 2-1 • Clock Spines Global Clock Networks (Trees) Clock Spines/Tree Total Spines Top or Bottom Spine Height (Tiles) Tiles in Each Top or Bottom Spine Total Tiles 2 -4 PAD RING APA075 APA150 APA300 512 ...
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... I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O Table 2-2 • Array Coordinates Logic Tile Min. Device x y APA075 1 1 APA150 1 1 APA300 1 5 APA450 1 5 APA600 1 5 APA750 1 5 APA1000 1 5 (1,169) ...
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PLUS ProASIC Flash Family FPGAs Input/Output Blocks To meet complex system demands, the ProASIC family offers devices with a large number of user I/O pins 712 on the APA1000. available supply voltage configurations (the PLL block uses an ...
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... DD PLUS V on ProASIC devices. Failure to follow these DDP guidelines may result in undesirable pin behavior during system start-up. For more information, refer to Actel’s PLUS Power-Up Behavior of ProASIC note. LVPECL Input Pads In addition to standard I/O pads and power pads, PLUS ProASIC ...
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... Boundary-Scan Opcodes EXTEST SAMPLE/PRELOAD IDCODE 2 -8 pins are dedicated for boundary-scan test usage. Actel recommends that a nominal 20 kΩ pull-up resistor is added to TDO and TCK pins. The TAP controller is a four-bit state machine (16 states) that operates as shown in 1s and 0s represent the values that must be present at TMS at a rising edge of TCK for the given state transition 2-9) ...
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The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller ...
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PLUS ProASIC Flash Family FPGAs Timing Control and Characteristics PLUS ProASIC Clock Management System PLUS ProASIC devices provide designers with very flexible clock conditioning capabilities. Each member of the PLUS ProASIC family contains two phase-locked loop (PLL) blocks which perform ...
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The clock conditioning circuit can advance or delay the clock (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock ...
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PLUS ProASIC Flash Family FPGAs Package Pins Physical I/O Buffers GL Std. Pad Cell NPECL PECL Pad Cell PPECL GLMX Std. Pad Cell GL Std. Pad Cell Legend Physical Pin DATA Signals to the Core DATA Signals to the PLL ...
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... The shift register can be accessed either from user logic within the device or via the JTAG port. Another option is internal dynamic configuration hardware. Refer to Actel's ProASIC Reconfiguration Using JTAG application note for more information. For information on the clock conditioning circuit, refer PLUS to Actel’ ...
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PLUS ProASIC Flash Family FPGAs Global MUX B OUT 33 MHz External Feedback Global MUX A OUT Figure 2-13 • Using the PLL 33 MHz In, 133 MHz Out Global MUX B OUT 40 MHz External Feedback Global MUX A ...
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Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Figure 2-15 • Using the PLL to Delay the Input Clock Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Figure 2-16 • Using the ...
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PLUS ProASIC Flash Family FPGAs On-Chip Off-Chip Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Reference Clock Figure 2-17 • Using the PLL for Clock Deskewing 180° ÷n PLL Core 0° ÷m ...
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... The derating factors shown in should be applied to all timing data contained within this datasheet. All timing numbers listed in this datasheet represent sample timing characteristics of ProASIC Actual timing delay values are design-specific and can be derived from the Timer tool in Actel’s Designer software after place-and-route. = 70° 2 0° ...
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PLUS ProASIC Flash Family FPGAs PLL Electrical Specifications Parameter Frequency Ranges Reference Frequency f (min.) IN Reference Frequency f (max.) IN OSC Frequency f (min.) VCO OSC Frequency f (max.) VCO Clock Conditioning Circuitry f (min.) OUT Clock Conditioning Circuitry ...
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... I/O Type PLL locking is guaranteed only when using low drive strength and low slew rate I/O. PLL locking may be inconsistent when using high drive strength or high slew rate I/Os SSO APA300 APA600 APA1000 APA300 APA600 APA1000 ProASIC ≤ T –40°C J ≤ ...
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... A single memory configuration could include blocks from both the top and bottom memory locations. PLUS Table 2-12 • ProASIC Memory Configurations by Device Device Bottom APA075 0 APA150 0 APA300 16 APA450 24 APA600 28 APA750 32 APA1000 Embedded Memory Configurations The embedded memory in the ProASIC ...
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Table 2-13 • Basic Memory Configurations Type Write Access RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Synchronous RAM Synchronous RAM Synchronous RAM Synchronous RAM Synchronous RAM Synchronous FIFO Asynchronous FIFO Asynchronous FIFO Asynchronous FIFO ...
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PLUS ProASIC Flash Family FPGAs DI <0:8> SRAM WADDR <0:7> (256x9) WRB WBLKB Sync Write WCLKS and Sync Read Ports WPE PARODD DI <0:8> SRAM WADDR <0:7> (256x9) WRB WBLKB Sync Write and WCLKS Async Read Ports WPE PARODD Note: ...
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DI<0:8> LEVEL<0:7> LGDEP<0:2> FIFO (256x9) WRB WBLKB Sync Write RDB and Sync Read RBLKB Ports PARODD WCLKS DI <0:8> LEVEL <0:7> FIFO LGDEP<0:2> (256x9) WRB WBLKB Async Write RDB and Sync Read RBLKB Ports PARODD Note: Each RAM block contains ...
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PLUS ProASIC Flash Family FPGAs Word Depth Figure 2-20 • APA1000 Memory Block Architecture Word Width Word 256 Depth 256 256 256 1,024 words x 9 bits, 1 read, 1 write Figure 2-21 • Example Showing Memory Arrays with Different ...
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... Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see Actel’s website for more information about ® IDE includes Synplify AE from Synplicity® ...
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... PLUS Using ProASIC Clock Conditioning Circuits http://www.actel.com/documents/APA_PLL_AN.pdf PLUS In-System Programming ProASIC http://www.actel.com/documents/APA_External_ISP_AN.pdf Performing Internal In-System Programming Using Actel’s ProASIC http://www.actel.com/documents/APA_Microprocessor_AN.pdf PLUS ProASIC RAM and FIFO Blocks http://www.actel.com/documents/APA_RAM_FIFO_AN.pdf White Paper Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity_WP.pdf User’ ...
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... Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) Ceramic Column Grid Array (CCGA/LGA) Notes: 1. Valid for the following devices irrespective of temperature grade: APA075, APA150, and APA300 2. Valid for the following devices irrespective of temperature grade: APA450, APA600, APA750, and APA1000 3. Depopulated array 4. Full array surface of the integrated circuit (IC) and is 110° ...
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... Total Power Consumption—P total total dc ac where for the APA075 for the APA150 11 mW for the APA300 12 mW for the APA450 12 mW for the APA600 13 mW for the APA750 19 mW for the APA1000 P includes the static components clock storage logic Global Clock Contribution— ...
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Logic-Tile Contribution—P logic P , the logic-tile component of AC power dissipation, is given by logic logic where: 1.4 μW/MHz is the average power consumption of a logic tile per MHz of its ...
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PLUS ProASIC Flash Family FPGAs The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. ...
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... FPGA below the worst-case performance indicated in the Actel Timer. To ensure that performance does not degrade below the worst-case values in the Actel Timer, the FPGA must be reprogrammed period. In addition, note that performance retention is independent of whether or not the FPGA is operating. ...
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PLUS ProASIC Flash Family FPGAs Table 2-19 • Military Temperature Grade Product Performance Retention Minimum Time at T Minimum Time 110°C or Below 125°C or Below 100% 90% 10% 75% 25% 90% 50% 50% 90% 75% 100% ...
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Table 2-20 • Recommended Maximum Operating Conditions Programming and PLL Supplies Parameter Condition V During Programming PP Normal Operation V During Programming PN Normal Operation I During Programming PP I During Programming PN AVDD AGND Notes: 1. Please refer to ...
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PLUS ProASIC Flash Family FPGAs Table 2-22 • DC Electrical Specifications (V Symbol Parameter V Output High Voltage OH High Drive (OB25LPH) Low Drive (OB25LPL) V Output Low Voltage OL High Drive (OB25LPH) Low Drive (OB25LPL Input High ...
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Table 2-22 • DC Electrical Specifications (V Symbol Parameter I Output Short Circuit Current Low OSL High Drive (OB25LPH) Low Drive (OB25LPL) C I/O Pad Capacitance I/O C Clock Input Pad Capacitance CLK Notes: 1. All process conditions. Commercial/Industrial: Junction ...
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PLUS ProASIC Flash Family FPGAs Table 2-23 • DC Electrical Specifications (V Applies to Commercial and Industrial Temperature Only Symbol Parameter V Output High Voltage OH 3.3 V I/O, High Drive (OB33P) 3.3 V I/O, Low Drive (OB33L) V Output ...
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Table 2-23 • DC Electrical Specifications (V Applies to Commercial and Industrial Temperature Only Symbol Parameter I Output Short Circuit Current OSH High 3.3 V High Drive (OB33P) 3.3 V Low Drive (OB33L) I Output Short Circuit Current OSL Low ...
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PLUS ProASIC Flash Family FPGAs Table 2-24 • DC Electrical Specifications (V Applies to Military Temperature and MIL-STD-883B Temperature Only Symbol Parameter V Output High Voltage OH 3.3 V I/O, High Drive, High Slew (OB33PH) 3.3V I/O, High Drive, Normal/ ...
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Table 2-24 • DC Electrical Specifications (V Applies to Military Temperature and MIL-STD-883B Temperature Only Symbol Parameter I Quiescent Supply Current DDQ (standby) Military I Tristate Output Leakage OZ Current I Output Short Circuit Current OSH High 3.3 V High ...
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PLUS ProASIC Flash Family FPGAs Table 2-25 • DC Specifications (3.3 V PCI Operation) Symbol Parameter V Supply Voltage for Core DD V Supply Voltage for I/O Ring DDP V Input High Voltage IH V Input Low Voltage IL 3 ...
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Table 2-26 • AC Specifications (3.3 V PCI Revision 2.2 Operation) Symbol Parameter Condition I Switching Current High 0 < V OH(AC) 0.3V 0.7V (Test Point) V OUT I Switching Current Low V OL(AC) DDP 0.6V 0.18V (Test Point) V ...
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PLUS ProASIC Flash Family FPGAs Tristate Buffer Delays A 50% 50 PAD 50 DLH DHL Figure 2-23 • Tristate Buffer Delays Table 2-27 • Worst-Case Commercial Conditions 2.3 ...
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Table 2-29 • Worst-Case Military Conditions load, T DDP DD Macro Type Description OTB33PH 3.3 V, PCI Output Current, High Slew Rate OTB33PN 3.3 V, High Output Current, Nominal Slew ...
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PLUS ProASIC Flash Family FPGAs Output Buffer Delays A Figure 2-24 • Output Buffer Delays Table 2-31 • Worst-Case Commercial Conditions load, T DDP DD Macro Type OB33PH 3.3 V, ...
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Table 2-33 • Worst-Case Military Conditions V = 3.0V 2.3V load, T DDP DD Macro Type Description OB33PL 3.3V, High Output Current, Low Slew Rate OB33LH 3.3V, Low Output Current, High Slew Rate OB33LN 3.3V, Low ...
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PLUS ProASIC Flash Family FPGAs Input Buffer Delays PAD Figure 2-25 • Input Buffer Delays Table 2-35 • Worst-Case Commercial Conditions DDP DD Macro Type IB33 3.3 V, CMOS Input Levels ...
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Table 2-37 • Worst-Case Military Conditions V = 3.0V 2.3V, T DDP DD Macro Type Description IB33 3.3 V, CMOS Input Levels IB33S 3.3 V, CMOS Input Levels Notes Input Pad-to-Y High INYH 2. t ...
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PLUS ProASIC Flash Family FPGAs Global Input Buffer Delays Table 2-39 • Worst-Case Commercial Conditions DDP DD Macro Type GL33 3.3 V, CMOS Input Levels GL33S 3.3 V, CMOS Input Levels ...
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Table 2-41 • Worst-Case Military Conditions V = 3.0V 2.3V, T DDP DD Macro Type GL33 3.3V, CMOS Input Levels GL33S 3.3V, CMOS Input Levels PECL PPECL Input Levels Notes Input Pad-to-Y High INYH 2. ...
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PLUS ProASIC Flash Family FPGAs Predicted Global Routing Delay Table 2-43 • Worst-Case Commercial Conditions DDP DD Parameter t Input Low to High RCKH t Input High to Low RCKL t ...
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Module Delays Figure 2-26 • Module Delays Sample Macrocell Library Listing Table 2-47 • Worst-Case Military Conditions 70º Cell Name NAND2 2-Input NAND AND2 2-Input AND ...
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PLUS ProASIC Flash Family FPGAs Table 2-48 • Recommended Operating Conditions Parameter Maximum Clock Frequency* Maximum RAM Frequency* Maximum Rise/Fall Time on Inputs* • Schmitt Trigger Mode (10% to 90%) • Non-Schmitt Trigger Mode (10% to 90%) Maximum LVPECL Frequency* ...
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Table 2-50 • JTAG Switching Characteristics Description Output delay from TCK falling to TDI, TMS TDO Setup time before TCK rising TDO Hold time after TCK rising TCK period RCK period Notes: 1. For DC electrical specifications of the JTAG ...
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PLUS ProASIC Flash Family FPGAs Embedded Memory Specifications PLUS This section discusses ProASIC SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks Table 2-13 on ...
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Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS RBD, RBLKB RADDR Note: The plot shows the normal operation status. Figure 2-28 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) Table 2-52 • 0°C to ...
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PLUS ProASIC Flash Family FPGAs Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS RDB, RBLKB New Valid RADDR Address DO RPE t RACS t RACH t RDCH t RDCS Note: The plot shows the normal operation status. Figure 2-29 ...
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Asynchronous SRAM Write WADDR WRB, WBLKB DI WPE t AWRS t WPDA Note: The plot shows the normal operation status. Figure 2-30 • Asynchronous SRAM Write Table 2-54 • 0°C to 110° 2 2.7 ...
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PLUS ProASIC Flash Family FPGAs Asynchronous SRAM Read, Address Controlled, RDB=0 RADDR DO RPE Note: The plot shows the normal operation status. Figure 2-31 • Asynchronous SRAM Read, Address Controlled, RDB = 0 Table 2-55 • 0°C to ...
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Table 2-56 • 0°C to 110° 2 2.7 V for Commercial/Industrial –55°C to 150° Symbol t Description xxx New DO access from RB ↓ ORDA Old DO ...
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PLUS ProASIC Flash Family FPGAs Synchronous SRAM Write WCLKS WRB, WBLKB WADDR, DI WPE t WRCH , t WBCH t WRCS , t WBCS t DCS , t WDCS t WPCH t DCH , t WACH Note: The plot shows ...
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Synchronous Write and Read to the Same Location RCLKS DO Last Cycle Data WCLKS t WCLKRCLKH t WCLKRCLKS t OCH t OCA ↑ Note: * New data is read if WCLKS occurs before setup time. The data stored is read ...
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PLUS ProASIC Flash Family FPGAs Asynchronous Write and Synchronous Read to the Same Location RCLKS Last Cycle Data {WRB + WBLKB WRCKS t BRCLKH t OCH t OCA t DWRRCLK ↓ Note: *New data is ...
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Asynchronous Write and Read to the Same Location RB, RADDR {WRB+WBLKB} t ORDA t ORDH t RAWRS Note: The plot shows the normal operation status. Figure 2-36 • Asynchronous Write and Read to the Same Location Table ...
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PLUS ProASIC Flash Family FPGAs Synchronous Write and Asynchronous Read to the Same Location RB, RADDR DO WCLKS t ORDA t ORDH t RAWCLKS Note: The plot shows the normal operation status. Figure 2-37 • Synchronous Write and Asynchronous Read ...
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Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem ...
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PLUS ProASIC Flash Family FPGAs FULL RB Write Write Inhibited Cycle WB Figure 2-38 • Write Timing Diagram EMPTY WB Read Read Inhibited Cycle RB Figure 2-39 • Read Timing Diagram ...
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Asynchronous FIFO Read RB = (RDB+RBLKB) RDATA EMPTY EQTH, GETH t RDWRS Note: The plot shows the normal operation status. Figure 2-40 • Asynchronous FIFO Read Table 2-63 • 0°C to 110° 2 2.7 ...
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PLUS ProASIC Flash Family FPGAs Asynchronous FIFO Write WB = (WRB + WBLKB) EQTH, GETH Note: The plot shows the normal operation status. Figure 2-41 • Asynchronous FIFO Write Table 2-64 • 0°C to 110° 2.3 ...
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Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLK RDB RDATA RPE EMPTY FULL EQTH, GETH Note: The plot shows the normal operation status. Figure 2-42 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) Table 2-65 • ...
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PLUS ProASIC Flash Family FPGAs Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK RDB RDATA RPE EMPTY FULL EQTH, GETH Note: The plot shows the normal operation status. Figure 2-43 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) ...
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Synchronous FIFO Write WCLKS WRB, WBLKB WPE FULL EMPTY EQTH, GETH t WRCH , t WBCH t WRCS , t WBCS Note: The plot shows the normal operation status. Figure 2-44 • Synchronous FIFO Write Table 2-67 • ...
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PLUS ProASIC Flash Family FPGAs FIFO Reset RESETB WRB/RBD WCLKS, RCLKS FULL EMPTY EQTH, GETH t ERSA , t FRSA t THRSA Notes: 1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be ...
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... DDP 2 3.3 V supply voltage. TMS The TMS pin controls the use of boundary-scan circuitry. This pin has an internal pull-up resistor. TCK Clock input pin for boundary scan (maximum 10 MHz). Actel recommends adding a nominal 20 kΩ pull-up resistor to this pin. and LVCMOS TDI Serial input for boundary scan ...
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... The same dual-capacitor circuit should be used on both the V V pins (Figure PN ProASIC APA300 to GND and V These devices do not require bypass capacitors on the and V pins as long as the total combined distance of PN ...
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... Package Pin Assignments 100-Pin TQFP 100 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 100-Pin TQFP v5.9 PLUS Flash Family FPGAs 3-1 ...
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PLUS ProASIC Flash Family FPGAs 100-Pin TQFP Pin APA075 APA150 Number Function Function 1 GND GND 2 I/O I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 GND GND ...
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... TQFP 144 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 144-Pin TQFP v5.9 PLUS Flash Family FPGAs 3-3 ...
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PLUS ProASIC Flash Family FPGAs 144-Pin TQFP Pin APA075 Number Function Number 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I GND 11 V DDP 12 I/O 13 I/O ...
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... PQFP 208 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 208-Pin PQFP v5.9 PLUS Flash Family FPGAs 3-5 ...
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... PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input 29 GND GND 30 I/O / GL1 I/O / GL1 31 I/O 32 I/O 33 I/O 34 I 208-Pin PQFP APA300 APA450 Function Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O 62 I/O I/O 63 I/O I/O 64 I/O I/O 65 GND GND 66 I/O I/O 67 I/O I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O 208-Pin PQFP APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I DDP DDP DDP GND GND GND ...
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... I/O 97 GND GND 98 I/O 99 I/O 100 I/O 101 TCK 102 TDI 103 TMS 104 V V DDP 105 GND GND 3 -8 208-Pin PQFP APA300 APA450 Function Function DDP DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O / GL4 I/O / GL4 135 I/O / GLMX2 I/O / GLMX2 136 I/O I/O 137 I/O I/O 138 V V DDP DDP 139 I/O I/O 140 I/O I/O 208-Pin PQFP APA300 APA450 APA600 Function Function Function TDO TDO TDO TRST TRST TRST RCK ...
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... I/O 167 I/O 168 I/O 169 I/O 170 V V DDP 171 V DD 172 I/O 173 I/O 174 I/O 175 I 208-Pin PQFP APA300 APA450 Function Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O I/O 204 I/O I/O 205 I/O I/O 206 I/O I/O 207 I/O I/O 208 V V DDP DDP 208-Pin PQFP APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O ...
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... Flash Family FPGAs 208-Pin CQFP No Ceramic Tie Bar Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx 208-Pin CQFP v5.9 156 155 154 153 142 141 140 139 138 137 136 135 134 108 107 106 105 ...
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... AVDD 28 PPECL1 / Input PPECL1 / Input PPECL1 / Input 29 GND GND 30 I/O / GL1 I/O / GL1 31 I/O I/O 32 I/O I/O 33 I/O I/O 34 I/O I/O 35 I/O I/O APA1000 Pin APA300 Function Number Function GND 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O ...
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... I/O 130 I/O 131 GND 132 I/O 133 I/O 134 I/O 135 TCK 136 TDI 137 TMS 138 V 139 DDP GND 140 v5.9 208-Pin CQFP APA300 APA600 APA1000 Function Function Function TDO TDO TDO TRST TRST TRST RCK RCK RCK ...
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... V V DDP DDP 171 172 I/O I/O 173 I/O I/O 174 I/O I/O 175 I/O I/O APA1000 Pin APA300 Function Number Function GND 176 V 177 DD I/O 178 I/O 179 I/O 180 I/O 181 I/O 182 I/O 183 I/O 184 I/O ...
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... Flash Family FPGAs 352-Pin CQFP Pin Ceramic Tie Bar Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx 352-Pin CQFP v5.9 264 263 262 261 223 222 221 220 219 218 217 216 215 180 179 178 177 ...
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... V V DDP DDP 32 I/O I/O 33 I/O I/O 34 I/O I/O 35 I/O I/O 36 I/O I/O 37 I/O I/O APA1000 APA300 Function Pin Number Function I/O 38 I/O / GLMX1 I/O 39 I/O / GL2 I/O 40 AGND I/O 41 AVDD I/O 42 NPECL1 I/O 43 PPECL1 / Input PPECL1 / Input PPECL1 / Input V 44 ...
Page 102
... DD DD I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 I/O 145 I/O 146 I/O 147 V 148 DDP v5.9 352-Pin CQFP APA300 APA600 APA1000 Function Function Function GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 103
... TDO 180 TRST TRST 181 RCK RCK 182 I/O I/O 183 V V DDP DDP 184 GND GND 185 APA1000 APA300 Function Pin Number Function I/O 186 I/O 187 I/O 188 I/O 189 I/O 190 I/O 191 V 192 DDP GND 193 V 194 DD ...
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... I/O 289 I/O 290 I/O 291 I/O 292 V 293 DDP GND 294 V 295 DD DD I/O 296 v5.9 352-Pin CQFP APA300 APA600 APA1000 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 105
... 329 GND GND 330 V V DDP DDP 331 I/O I/O 332 I/O I/O 333 I/O I/O APA1000 APA300 Function Pin Number Function V 334 DDP I/O 335 I/O 336 I/O 337 I/O 338 I/O 339 I/O 340 I/O 341 I/O 342 ...
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... PLUS ProASIC Flash Family FPGAs 456-Pin PBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx v5.9 A1 Ball Pad Corner ...
Page 107
... Pin APA150 APA300 Number Function Function A1 V DDP A2 V DDP I/O A9 I/O A10 I/O A11 I/O A12 I/O A13 I/O A14 I/O A15 I/O A16 I/O A17 I/O A18 I/O A19 I/O A20 NC A21 NC A22 NC A23 NC A24 NC A25 V DDP A26 V DDP ...
Page 108
... C7 I/O C8 I/O C9 I/O C10 I/O C11 I/O C12 I/O C13 I/O C14 I/O C15 I/O C16 I 456-Pin PBGA APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 109
... Pin APA150 APA300 Number Function Function C17 I/O C18 I/O C19 I/O C20 I/O C21 NC C22 NC C23 NC C24 V DDP C25 NC C26 DDP I/O D8 I/O D9 I/O D10 I/O D11 I/O D12 I/O D13 I/O D14 I/O D15 I/O D16 I/O D17 I/O ...
Page 110
... E16 I/O E17 I/O E18 I/O E19 I/O E20 V DD E21 V DD E22 V DD E23 NC E24 NC E25 NC E26 F22 456-Pin PBGA APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O ...
Page 111
... Pin APA150 APA300 Number Function Function F23 NC F24 NC F25 NC F26 NC G1 I G22 V DD G23 NC G24 NC G25 NC G26 I/O H1 I/O H2 I/O H3 I H22 V DD H23 I/O H24 I/O H25 I/O H26 I/O J1 I/O J2 I/O J3 I/O J4 I/O J5 I/O J22 I/O ...
Page 112
... L25 I/O L26 I/O M1 I/O / GL1 M2 I/O / GL2 M3 I/O M4 I/O M5 I/O M11 GND M12 GND M13 GND 456-Pin PBGA APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 113
... Pin APA150 APA300 Number Function Function M14 GND M15 GND M16 GND M22 I/O / GL4 I/O / GL4 M23 I/O M24 I/O M25 I/O M26 I/O N1 I/O N2 I/O / GLMX1 I/O / GLMX1 N3 AGND N4 PPECL1 / Input PPECL1 / Input N5 AVDD N11 GND N12 GND N13 ...
Page 114
... T4 I/O T5 I/O T11 GND T12 GND T13 GND T14 GND T15 GND T16 GND T22 I 456-Pin PBGA APA300 APA450 Function Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O PPECL2 / Input PPECL2 / Input PPECL2 / Input I/O I/O I/O I/O ...
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... Pin APA150 APA300 Number Function Function T23 I/O T24 I/O T25 I/O T26 I/O U1 I/O U2 I/O U3 I/O U4 I/O U5 I/O U22 I/O U23 I/O U24 I/O U25 I/O U26 I/O V1 I/O V2 I/O V3 I/O V4 I/O V5 I/O V22 I/O V23 I/O V24 I/O V25 ...
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... AB4 NC AB5 V DD AB6 V DD AB7 V DD AB8 I/O AB9 I/O AB10 I/O AB11 I/O AB12 I/O AB13 I/O AB14 I 456-Pin PBGA APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O ...
Page 117
... Pin APA150 APA300 Number Function Function AB15 I/O AB16 I/O AB17 I/O AB18 I/O AB19 I/O AB20 V DD AB21 V DD AB22 V DD AB23 NC AB24 NC AB25 NC AB26 NC AC1 NC AC2 NC AC3 NC AC4 V DDP AC5 NC AC6 I/O AC7 I/O AC8 I/O AC9 I/O AC10 ...
Page 118
... I/O AD19 I/O AD20 NC AD21 TCK AD22 V PP AD23 NC AD24 V DDP AD25 NC AD26 NC AE1 V DDP AE2 V DDP AE3 NC AE4 456-Pin PBGA APA300 APA450 APA600 Function Function Function V V DDP DDP RCK RCK NC I/O I/O I I/O I DDP DDP NC I/O NC I/O NC I/O I/O ...
Page 119
... Pin APA150 APA300 Number Function Function AE5 NC AE6 NC AE7 NC AE8 I/O AE9 I/O AE10 I/O AE11 I/O AE12 I/O AE13 I/O AE14 I/O AE15 I/O AE16 I/O AE17 I/O AE18 I/O AE19 I/O AE20 NC AE21 NC AE22 NC AE23 V PN AE24 TRST AE25 ...
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... I/O AF16 I/O AF17 I/O AF18 NC AF19 NC AF20 NC AF21 NC AF22 NC AF23 TDI AF24 NC AF25 V DDP AF26 V DDP 456-Pin PBGA APA300 APA450 APA600 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O NC I/O NC I/O NC I/O TDI ...
Page 121
... FBGA 12 11 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-37 ...
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... I/O I/O F9 I/O I/O F10 I/O I/O F11 I/O I/O F12 I/O I/O I/O I/O v5.9 144-FBGA Pin APA075 APA150 APA300 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 123
... M9 I/O I/O M10 TDO TDO M11 I/O I/O M12 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 144-FBGA Pin APA075 APA150 APA300 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 124
... PLUS ProASIC Flash Family FPGAs 256-Pin FBGA 16 15 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner v5 ...
Page 125
... I/O I/O E2 I/O I/O E3 I/O I/O E4 I/O I/O E5 I/O I/O E6 v5.9 PLUS ProASIC Flash Family FPGAs 256-Pin FBGA APA150 APA300 APA450 APA600 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O I/O J5 I/O I/O J6 I/O I DDP DDP GND GND J10 GND GND J11 GND GND v5.9 256-Pin FBGA APA150 APA300 APA450 Function Function Function GND GND GND DDP DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 127
... DD DD N13 GND GND N14 V V DDP DDP N15 I/O I/O N16 v5.9 PLUS ProASIC Flash Family FPGAs 256-Pin FBGA APA150 APA300 APA450 APA600 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O I/O I/O I/O I/O TDI TDI TDO TDO GND GND I/O I/O I/O I/O v5.9 256-Pin FBGA APA150 APA300 APA450 APA600 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 129
... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-45 ...
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PLUS ProASIC Flash Family FPGAs 484-Pin FBGA Pin APA450 APA600 Number Function Function A1 GND GND A2 GND GND DDP DDP A4 I/O I/O A5 I/O I/O A6 I/O I/O A7 I/O I/O A8 I/O I/O A9 ...
Page 131
FBGA Pin APA450 APA600 Number Function Function E21 I/O I/O E22 I/O I/O F1 I/O I/O F2 I/O I/O F3 I/O I/O F4 I/O I/O F5 I/O I/O F6 I/O I/O F7 I/O I/O F8 I/O I/O F9 I/O ...
Page 132
PLUS ProASIC Flash Family FPGAs 484-Pin FBGA Pin APA450 APA600 Number Function Function K19 I/O I/O K20 I/O I/O K21 I/O I/O K22 I/O I I/O L2 I/O I/O L3 I/O I/O L4 I/O / GL1 I/O / ...
Page 133
FBGA Pin APA450 APA600 Number Function Function R15 I/O I/O R16 I/O I/O R17 I/O I/O R18 I/O I/O R19 I/O I/O R20 R21 I/O I/O R22 I/O I/O T1 I/O I/O T2 I/O I/O ...
Page 134
PLUS ProASIC Flash Family FPGAs 484-Pin FBGA Pin APA450 APA600 Number Function Function Y13 I/O I/O Y14 Y15 Y16 I/O I/O Y17 I/O I/O Y18 GND GND Y19 I/O I/O Y20 I/O ...
Page 135
... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx v5.9 PLUS ProASIC Flash Family FPGAs A1 Ball Pad Corner 3-51 ...
Page 136
PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function A1 GND GND A2 GND GND A3 I/O I/O A4 I/O I/O A5 I/O I/O A6 I/O I/O A7 I/O I/O A8 I/O I/O A9 I/O I/O ...
Page 137
FBGA Pin APA600 APA750 Number Function Function E2 I/O I/O E3 I/O I/O E4 I/O I/O E5 I/O I/O E6 I/O I/O E7 I/O I/O E8 I/O I/O E9 I/O I/O E10 I/O I/O E11 I/O I/O E12 I/O ...
Page 138
PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function J3 I/O I/O J4 I/O I/O J5 I/O I/O J6 I/O I DDP DDP J10 V ...
Page 139
FBGA Pin APA600 APA750 Number Function Function N4 I/O I/O N5 NPECL1 NPECL1 N6 I/O I DDP DDP N10 GND GND N11 GND GND N12 GND GND N13 ...
Page 140
PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function U3 I/O I/O U4 I/O I/O U5 I/O I/O U6 I/O I DDP DDP U10 GND ...
Page 141
FBGA Pin APA600 APA750 Number Function Function AA4 I/O I/O AA5 I/O I/O AA6 GND GND AA7 I/O I/O AA8 I/O I/O AA9 I/O I/O AA10 I/O I/O AA11 I/O I/O AA12 I/O I/O AA13 I/O I/O AA14 I/O ...
Page 142
PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function AE5 I/O I/O AE6 I/O I/O AE7 I/O I/O AE8 I/O I/O AE9 I/O I/O AE10 I/O I/O AE11 I/O I/O AE12 I/O I/O AE13 I/O I/O ...
Page 143
... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-59 ...
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PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function A2 GND GND A3 GND GND A4 I/O I/O A5 GND GND A6 I/O I/O A7 GND GND A8 I/O I/O A9 I/O I/O A10 I/O I/O ...
Page 145
FBGA Pin APA750 APA1000 Number Function Function D15 I/O I/O D16 I/O I/O D17 I/O I/O D18 I/O I/O D19 I/O I/O D20 I/O I/O D21 I/O I/O D22 I/O I/O D23 I/O I/O D24 I/O I/O D25 I/O ...
Page 146
PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function G27 I/O I/O G28 I/O I/O G29 I/O I/O G30 GND GND H1 I/O I/O H2 I/O I/O H3 I/O I/O H4 I/O I/O H5 I/O I/O ...
Page 147
FBGA Pin APA750 APA1000 Number Function Function L9 NC I/O L10 NC I/O L11 L12 L13 L14 L15 L16 ...
Page 148
PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function P21 V V DDP DDP P22 I/O I/O P23 I/O I/O P24 I/O I/O P25 I/O I/O P26 I/O I/O P27 I/O I/O P28 I/O I/O P29 ...
Page 149
FBGA Pin APA750 APA1000 Number Function Function V3 I/O I/O V4 I/O I/O V5 I/O I/O V6 I/O I/O V7 I/O I/O V8 I/O I I/O V10 V V DDP DDP V11 V12 ...
Page 150
PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function AA15 V V DDP DDP AA16 V V DDP DDP AA17 V V DDP DDP AA18 V V DDP DDP AA19 V V DDP DDP AA20 NC ...
Page 151
FBGA Pin APA750 APA1000 Number Function Function AD27 I/O I/O AD28 I/O I/O AD29 I/O I/O AD30 GND GND AE1 I/O I/O AE2 AE3 I/O I/O AE4 I/O I/O AE5 I/O I/O AE6 GND GND ...
Page 152
PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function AH9 I/O I/O AH10 I/O I/O AH11 I/O I/O AH12 I/O I/O AH13 I/O I/O AH14 I/O I/O AH15 I/O I/O AH16 I/O I/O AH17 I/O I/O ...
Page 153
... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-69 ...
Page 154
PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function Number GND A4 GND A5 GND A6 I A10 V DD A11 I/O A12 GND A13 I/O ...
Page 155
FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number E15 I/O F18 E16 I/O F19 E17 I/O F20 E18 I/O F21 E19 I/O F22 E20 I/O F23 E21 I/O F24 E22 I/O F25 E23 I/O F26 E24 I/O F27 ...
Page 156
PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function Number J27 I/O J28 V DDP J29 I/O J30 I/O J31 I/O J32 GND J33 I/O J34 I/O K4 I/O K5 ...
Page 157
FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number I/O R10 P8 I/O R11 P9 I/O R12 P10 I/O R13 P11 I/O R14 P12 V R15 DDP P13 V R16 DD P14 ...
Page 158
PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function Number V16 GND V17 GND V18 GND V19 GND V20 GND V21 GND V22 V DD V23 V DDP V24 I/O V25 I/O V26 I/O V27 I/O V28 PPECL2 ...
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FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number AB27 I/O AC30 AB28 I/O AC31 AB29 I/O AC32 AB30 I/O AC33 AB31 I/O AC34 AB32 I/O AD1 AB33 I/O AD2 AB34 I/O AD3 AC1 GND AD4 AC2 GND AD5 ...
Page 160
PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function Number AG5 I/O AG6 I/O AG7 I/O AH10 AG8 GND AH11 AG9 I/O AH12 AG10 I/O AH13 AG11 I/O AH14 AG12 I/O AH15 AG13 I/O AH16 AG14 I/O AH17 ...
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FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number AL17 I/O AM20 AL18 I/O AM21 AL19 I/O AM22 AL20 I/O AM23 AL21 I/O AM24 AL22 I/O AM25 AL23 I/O AM26 AL24 I/O AM27 AL25 I/O AM28 AL26 I/O AM29 ...
Page 162
... PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA 101112131415 161718 19 20 2122 23 25 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx Top View D A1 Corner Index Area Bottom View v5 Side View ...
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CCGA/LGA Pin APA600 APA1000 Number Function Function A2 I/O I/O A3 I/O I/O A4 I/O I/O A5 I/O I/O A6 I/O I/O A7 I/O I/O A8 I/O I/O A9 I/O I/O A10 I/O I/O A11 I/O I/O A12 I/O ...
Page 164
PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function E7 I/O I/O E8 I/O I/O E9 I/O I/O E10 I/O I/O E11 I/O I/O E12 I/O I/O E13 I/O I/O E14 I/O I/O E15 I/O I/O ...
Page 165
CCGA/LGA Pin APA600 APA1000 Number Function Function J12 GND GND J13 GND GND J14 GND GND J15 GND GND J16 GND GND J17 GND GND J18 V V DDP DDP J19 I/O I/O J20 GND GND J21 I/O I/O ...
Page 166
PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function N16 N17 GND GND N18 V V DDP DDP N19 I/O I/O N20 I/O / GL3 I/O / GL3 N21 PPECL2 / PPECL2 ...
Page 167
CCGA/LGA Pin APA600 APA1000 Number Function Function U20 GND GND U21 I/O I/O U22 I/O I/O U23 I/O I/O U24 I/O I/O U25 I/O I/O V1 I/O I/O V2 I/O I/O V3 GND GND V4 I/O I/O V5 I/O ...
Page 168
PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function AA25 I/O I/O AB1 I/O I/O AB2 I/O I/O AB3 I/O I/O AB4 I/O I/O AB5 I/O I/O AB6 I/O I/O AB7 I/O I/O AB8 I/O I/O ...
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... The heading, MIL-STD-883B, and note 4 were added to the (May 2006) The "Temperature Grade Offerings" table grade in the following device/packages: APA300-FG144 APA300-FG256 APA600-FG256 APA600-FG484 APA600-FG676 APA1000-FG896 v5.2 90° and 270° phase shift support was removed from the datasheet. (December 2005) The " ...
Page 170
PLUS ProASIC Flash Family FPGAs Previous version Changes in current version (v5.9) v5.1 MIL-STD-883 was added to the datasheet. V and V were changed CCI Table 2-9 • Temperature and Voltage Derating Factors v5.0 In the "208-Pin ...
Page 171
Previous version Changes in current version (v5.9) v4.1 Figure 2-27 • JTAG Operation Timing (continued) Note 1 in Table 2-52 • T updated. The notes in Table 2-56 • T were updated. A note was added to A note was ...
Page 172
PLUS ProASIC Flash Family FPGAs Previous version Changes in current version (v5.9) PLUS v3.2 The "ProASIC Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram Table 2-7 • Clock-Conditioning Circuitry MUX Settings Figure 2-17 • Using ...
Page 173
Previous version Changes in current version (v5.9) v2.0 The following pins have been changed in the (continued) Pin Number "144-Pin TQFP" section The following pins have been changed in the Pin Number ...
Page 174
PLUS ProASIC Flash Family FPGAs Previous version Changes in current version (v5.9) v2.0 The following pins have been changed in the (continued) Pin Number PLUS Advance v0.7 The "ProASIC The "Array Coordinates" section The "Power-Up ...
Page 175
Previous version Changes in current version (v5.9) Advance v0.6 The "Calculating Typical Power Dissipation" section (continued) The "Absolute Maximum Ratings*" section The "Programming, Storage, and Operating Limits" section The "Nominal Supply Voltages’ section was updated. The "Recommended Operating Conditions" section ...
Page 176
... All pinout tables have been updated, and several packages are new: 208-Pin PQFP – APA150, APA300, APA450, APA600 456-Pin PBGA – APA150, APA300, APA450, APA600 144-Pin FBGA – APA150, APA300, APA450 256-Pin FBGA – APA150, APA300, APA450, APA600 676-Pin FBGA – APA600 Advance v0.1 Figure 2-20 • APA1000 Memory Block Architecture ...
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...
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... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. ...