A42MX16-TQG176 Actel, A42MX16-TQG176 Datasheet - Page 30

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A42MX16-TQG176

Manufacturer Part Number
A42MX16-TQG176
Description
FPGA - Field Programmable Gate Array 24K System Gates
Manufacturer
Actel
Datasheet

Specifications of A42MX16-TQG176

Processor Series
A42MX16
Core
IP Core
Number Of Macrocells
608
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
140
Delay Time
5.6 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
3 V
Number Of Gates
24 K
Package / Case
TQFP-176
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
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A42MX16-TQG176
Manufacturer:
Actel
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Manufacturer:
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Quantity:
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A42MX16-TQG176A
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Part Number:
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Manufacturer:
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Quantity:
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Notes: * Values are shown for A42MX36 ‘–3’ at 5.0V worst-case commercial conditions.
Figure 1-19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)
Note: *Values are shown for A42MX36 ‘–3 at 5.0V worst-case commercial conditions.
Figure 1-20 • 42MX Timing Model (SRAM Functions)
1 -2 4
40MX and 42MX FPGA Families
** Load-dependent
Clocks
Array
Clocks
Array
I/O Module
F
MAX
I/O Module
t
t INSU=0.3 ns
t INGL=1.3 ns
INH=0.0 ns
F
Input Delays
MAX=296 MHz
=167 MHz
t CKH=2.70 ns
t INSU=0.5ns
t INH=0.0ns
t INGO=1.4ns
t INPY=1.0ns
D
G
Input Delays
D
G
t
INYL=0.8 ns
Q
Q
FO = 32
t IRD1=2.0ns
t IRD1=2.0 ns
t ADSU=1.6ns
t ADH=0.0ns
t WENSU=2.7ns
t BENS=2.8ns
WD [7:0]
WRAD [5:0]
BLKEN
WEN
WCLK
t SUD=0.3 ns
t HD=0.00 ns
t LCO=5.2 ns (light loads, pad-to-pad)
Combin
-atoria l
include
Internal Delays
Logic
Combinatorial
Logic Module
t PD=1.2 ns
Logic Module
Sequential
v6.1
RDAD [5:0]
t ADSU=1.6ns
t ADH=0.0ns
t RENSU=0.6ns
t RCO=3.4ns
RD [7:0]
RCLK
t CO=1.3 ns
REN
D
Q
t
t RD2=1.9 ns
t RD4=1.4 ns
t RD8=2.3 ns
Predicted
RD1=0.7 ns
Routing
Delays
t RD1=0.70 ns
t RD1=0.9ns
Predicted
Routing
Delays
I/O Module
I/O Module
t OUTH=0.00 ns
t OUTSU=0.3 ns
t
GLH=2.6 ns
D
Output Delays
G
Q
t DLH=2.5 ns
t DLH=2.5 ns
t GHL=2.9ns
t LSU=0.5ns
t LH=0.0ns
I/O Module
t ENHZ=4.9 ns
t DLH=2.6ns
D
G
Q

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