AGL1000V2-FGG144 Actel, AGL1000V2-FGG144 Datasheet - Page 42
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AGL1000V2-FGG144
Manufacturer Part Number
AGL1000V2-FGG144
Description
FPGA - Field Programmable Gate Array 1M System Gates IGLOO
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL1000V2-FGG144
Processor Series
AGL1000
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
147456
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
1 M
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL1000V2-FGG144
Manufacturer:
Actel
Quantity:
135
Company:
Part Number:
AGL1000V2-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL1000V2-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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IGLOO DC and Switching Characteristics
Table 2-28 • Summary of AC Measuring Points
Table 2-29 • I/O AC Parameter Definitions
2- 28
Summary of I/O Timing Characteristics – Default I/O Software Settings
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V VCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
3.3 V PCI
3.3 V PCI-X
Parameter
t
t
t
t
t
t
t
t
t
t
t
DP
PY
DOUT
EOUT
DIN
HZ
ZH
LZ
ZL
ZHS
ZLS
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
Enable to Pad delay through the Output Buffer—Z to Low
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
Parameter Definition
R ev i sio n 1 8
Measuring Trip Point (Vtrip)
0.285 * VCCI (RR)
0.285 * VCCI (RR)
0.615 * VCCI (FF)
0.615 * VCCI (FF)
0.60 V
0.60 V
0.90 V
0.75 V
1.4 V
1.4 V
1.2 V
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