A3P600L-PQG208 Actel, A3P600L-PQG208 Datasheet - Page 30
A3P600L-PQG208
Manufacturer Part Number
A3P600L-PQG208
Description
FPGA - Field Programmable Gate Array 6K SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P600L-PQG208
Processor Series
A3P600
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
154
Data Ram Size
110592
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P600L-PQG208
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3P600L-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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ProASIC3L DC and Switching Characteristics
2- 16
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding
contribution (P
Combinatorial Cells Contribution—P
Routing Net Contribution—P
I/O Input Buffer Contribution—P
I/O Output Buffer Contribution—P
RAM Contribution—P
PLL Contribution—P
P
F
P
P
P
P
P
CLK
C-CELL
NET
INPUTS
OUTPUTS
MEMORY
PLL
AC13
N
α
page
N
N
α
page
F
N
α
F
N
α
β
F
N
F
β
F
β
page
= P
F
is the global clock signal frequency.
= (N
* F
CLK
CLK
CLK
READ-CLOCK
WRITE-CLOCK
CLKOUT
1
2
3
C-CELL
S-CELL
C-CELL
INPUTS
OUTPUTS
BLOCKS
1
1
2
2
= N
= N
is the I/O buffer enable rate—guidelines are provided in
is the RAM enable rate for read operations.
DC4
is the RAM enable rate for write operations—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
CLKOUT
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
S-CELL
= P
= N
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
2-17.
2-17.
2-17.
C-CELL
INPUTS
+ P
AC11
OUTPUTS
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of I/O input buffers used in the design.
is the output clock frequency.
is the number of RAM blocks used in the design.
product) to the total PLL contribution.
AC13
is the number of I/O output buffers used in the design.
+ N
*
* N
*
α
is the memory read clock frequency.
C-CELL
is the memory write clock frequency.
α
PLL
*F
BLOCKS
1
MEMORY
2
/ 2 * P
*
CLKOUT
/ 2 * P
α
) *
2
/ 2 *
AC7
* F
α
NET
AC9
1
READ-CLOCK
β
/ 2 * P
* F
INPUTS
* F
1
CLK
* P
OUTPUTS
CLK
AC8
AC10
C-CELL
R e visio n 9
* F
* F
*
1
CLK
β
CLK
2
+ P
AC12
* N
BLOCK
Table 2-20 on page
Table 2-20 on page
Table 2-21 on page
* F
WRITE-CLOCK
*
Table 2-20 on
Table 2-20 on
β
Table 2-21 on
3
2-17.
2-17.
2-17.
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