LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 3
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LFXP3C-3TN144I
Manufacturer Part Number
LFXP3C-3TN144I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
Manufacturer
Lattice
Specifications of LFXP3C-3TN144I
Number Of Programmable I/os
100
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Package
144TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
100
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
INTEL
Quantity:
1 143
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Introduction
Lattice Semiconductor
LatticeXP Family Data Sheet
Introduction
The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/Os in a
single architecture that is both non-volatile and infinitely reconfigurable to support cost-effective system designs.
The re-programmable non-volatile technology used in the LatticeXP family is the next generation ispXP™ technol-
ogy. With this technology, expensive external configuration memories are not required and designs are secured
from unauthorized read-back. In addition, instant-on capability allows for easy interfacing in many applications.
®
The ispLEVER
design tool from Lattice allows large complex designs to be efficiently implemented using the Lat-
ticeXP family of FPGA devices. Synthesis library support for LatticeXP is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and back-
annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeXP family.
By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
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