LFXP2-8E-5TN144C Lattice, LFXP2-8E-5TN144C Datasheet - Page 3

• Manufacturer Part Number: LFXP2-8E-5TN144C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice
• Series: LatticeXP2r

Specifications of LFXP2-8E-5TN144C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• No. Of Logic Blocks: 8000
• No. Of Macrocells: 4000
• Family Type: LatticeXP2
• No. Of Speed Grades: 5
• Total Ram Bits: 221Kbit
• No. Of I/o's: 100
• Clock Management: PLL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Introduction
Lattice Semiconductor
LatticeXP2 Family Data Sheet
Introduction
LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architec-
ture referred to as flexiFLASH.
The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with
FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live
Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies.
The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low
cost in mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked
Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks.
®
The ispLEVER
design tool from Lattice allows large and complex designs to be efficiently implemented using the
LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis
tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to
place and route the design in the LatticeXP2 device. The ispLEVER tool extracts the timing from the routing and
back-annotates it into the design for timing verification.
Lattice provides many pre-designed Intellectual Property (IP) ispLeverCORE™ modules for the LatticeXP2 family.
By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
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