AGL1000V2-FGG256 Actel, AGL1000V2-FGG256 Datasheet - Page 31
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AGL1000V2-FGG256
Manufacturer Part Number
AGL1000V2-FGG256
Description
FPGA - Field Programmable Gate Array 1M System Gates IGLOO
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL1000V2-FGG256
Processor Series
AGL1000
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
177
Data Ram Size
147456
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
1 M
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software.
The power calculation methodology described below uses the following variables:
Methodology
Total Power Consumption—P
Total Static Power Consumption—P
Total Dynamic Power Consumption—P
Global Clock Contribution—P
Sequential Cells Contribution—P
•
•
•
•
•
•
•
•
P
P
P
P
P
TOTAL
STAT
DYN
CLOCK
S-CELL
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
page
Enable rates of output buffers—guidelines are provided for typical applications in
page
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-23 on page
the design.
P
P
N
N
N
N
Table 2-22 on page
N
Table 2-22 on page
F
N
P
N
multi-tile sequential cell is used, it should be accounted for as 1.
α
page
F
= P
= (P
CLK
AC1
CLK
STAT
DYN
INPUTS
OUTPUTS
BANKS
SPINE
ROW
S-CELL
S-CELL
1
= P
= (P
= N
2-19.
2-19.
CLOCK
is the toggle rate of VersaTile outputs—guidelines are provided in
DC1
, P
STAT
is the global clock signal frequency.
is the global clock signal frequency.
2-19.
is the total dynamic power consumption.
S-CELL
is the total static power consumption.
AC1
is the number of VersaTile rows used in the design—guidelines are provided in
AC2
is the number of global spines used in the user design—guidelines are provided in
is the number of I/O banks powered in the design.
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as sequential modules in the design. When a
is the number of I/O input buffers used in the design.
or P
+ P
+ P
+ N
is the number of I/O output buffers used in the design.
, P
DC2
* (P
DYN
S-CELL
AC3
SPINE
AC5
or P
, and P
2-19. The calculation should be repeated for each clock domain defined in
* P
2-19.
2-19.
+ P
+
DC3
AC2
α
C-CELL
1
) + N
AC4
TOTAL
CLOCK
/ 2 * P
+ N
are device-dependent.
S-CELL
BANKS
ROW
+ P
AC6
STAT
R ev i si o n 1 8
NET
* P
) * F
* P
DYN
AC3
+ P
DC5
CLK
+ N
INPUTS
+ N
S-CELL
INPUTS
+ P
* P
OUTPUTS
* P
AC4
DC6
) * F
+ N
+ P
CLK
OUTPUTS
MEMORY
IGLOO Low Power Flash FPGAs
+ P
* P
DC7
PLL
Table 2-22 on
Table 2-22 on
Table 2-23 on
2- 17
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