LFE2-6E-6FN256C Lattice, LFE2-6E-6FN256C Datasheet - Page 107
LFE2-6E-6FN256C
Manufacturer Part Number
LFE2-6E-6FN256C
Description
FPGA - Field Programmable Gate Array 6K LUTs 190 I/O DSP 1.2V -6
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2-6E-6FN256C
Number Of Macrocells
6000
Number Of Programmable I/os
190
Data Ram Size
56320
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-6E-6FN256C
Manufacturer:
Lattice
Quantity:
118
Company:
Part Number:
LFE2-6E-6FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFE2-6E-6FN256C-5I
Manufacturer:
LATTICE
Quantity:
64
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Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
For Left and Right Edges of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
For Bottom Edge of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
P[Edge] [n+4]
Notes:
1. “n” is a row PIC number.
2. The DDR interface is designed for memories that support one DQS strobe up to 15 bits
PICs Associated with
of data for the left and right edges and up to 17 bits of data for the bottom edge. In some
packages, all the potential DDR data (DQ) pins may not be available. PIC numbering
definitions are provided in the “Signal Names” column of the Signal Descriptions table.
DQS Strobe
PIO Within PIC
4-4
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DDR Strobe (DQS) and
LatticeECP2/M Family Data Sheet
Data (DQ) Pins
[Edge]DQSn
[Edge]DQSn
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Pinout Information
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